MIPSProcessorEx2.qsf

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#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other 
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#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 19:27:10  June 26, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		MIPSProcessorEx2_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY MIPS_Processor
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:27:09  JUNE 26, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
set_global_assignment -name VERILOG_FILE sources/SignExtend.v
set_global_assignment -name VERILOG_FILE sources/ShiftLeft2.v
set_global_assignment -name VERILOG_FILE sources/RegisterFile.v
set_global_assignment -name VERILOG_FILE sources/Register.v
set_global_assignment -name VERILOG_FILE sources/ProgramMemory.v
set_global_assignment -name VERILOG_FILE sources/PC_Register.v
set_global_assignment -name VERILOG_FILE sources/ORGate.v
set_global_assignment -name VERILOG_FILE sources/MUXRegisterFile.v
set_global_assignment -name VERILOG_FILE sources/Multiplexer2to1.v
set_global_assignment -name VERILOG_FILE sources/MIPS_Processor_TB.v
set_global_assignment -name VERILOG_FILE sources/MIPS_Processor.v
set_global_assignment -name VERILOG_FILE sources/DecoderRegisterFile.v
set_global_assignment -name VERILOG_FILE sources/DataMemory.v
set_global_assignment -name VERILOG_FILE sources/Control.v
set_global_assignment -name VERILOG_FILE sources/ANDGate.v
set_global_assignment -name VERILOG_FILE sources/ALUControl.v
set_global_assignment -name VERILOG_FILE sources/ALU.v
set_global_assignment -name VERILOG_FILE sources/Adder32bits.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"