refactor: Update RAM.v and TM.v to fix bugs and improve code readability

Author: 0857boy

code/Conv.v

@@ -8,16 +8,26 @@ module Conv(
     output reg out_st
 );
 
+////////////////////////////////Load Data////////////////////////////
 reg start_conv, load_data_status;
-reg [15:0] conv_result [0:35];
 reg [7:0] input_feature [0:63];
-reg cycle ;
-reg [2:0] line, row;
-reg [15:0] temp[0:8];
 reg [5:0] data_counter ;
+////////////////////////////////////////////////////////////////////
+
+////////////////////////////////Convolution/////////////////////////
+reg [19:0] conv_result [0:35]; // 原來是 20 bits ， 但我們只取 16 bits(6,10)fixed point
+reg [19:0] temp[0:8];
+reg [2:0] line, row;
+reg cycle ;
+////////////////////////////////////////////////////////////////////
+
 
+///////////////////////////////Output///////////////////////////////
+reg [5:0] output_counter ;
+reg output_data_status;
+////////////////////////////////////////////////////////////////////
 
-// 3x3 fixed-point kernel
+////////////////////////////////Fixed-point Kernel///////////////////
 reg [7:0] fixed_kernel [0:8] ;
 initial begin
     fixed_kernel[0] = 8'b00001000; // 0.0625 -> 00001000
@@ -29,15 +39,22 @@ initial begin
     fixed_kernel[6] = 8'b00001000; // 0.0625 -> 00001000
     fixed_kernel[7] = 8'b00010000; // 0.125  -> 00010000
     fixed_kernel[8] = 8'b00001000; // 0.0625 -> 00001000
-
-    start_conv = 1'b0;
-    load_data_status = 1'b0;
-    cycle = 1'b0;
-    line = 3'b000;
-    row = 3'b000;
-    data_counter = 6'b000000;
-    out_st = 1'b0;
 end								   
+////////////////////////////////////////////////////////////////////
+
+////////////////////////////////initial/////////////////////////////
+initial begin
+    start_conv <= 1'b0;
+    load_data_status <= 1'b0;
+    data_counter <= 6'b000000;
+    line <= 3'b000;
+    row <= 3'b000;
+    cycle <= 1'b0;
+    out_st <= 1'b0;
+    output_counter <= 6'b000000;
+    output_data_status <= 1'b0;
+end
+////////////////////////////////////////////////////////////////////
 
 always @(posedge clk) begin
 
@@ -48,6 +65,16 @@ always @(posedge clk) begin
             data_counter <= 6'b000000; 
             load_data_status <= 1'b0;
             start_conv <= 1'b1;
+            $display("Input Feature Get From RAM: ");
+            $display(" %b %b %b %b %b %b %b %b", input_feature[0], input_feature[1], input_feature[2], input_feature[3], input_feature[4], input_feature[5], input_feature[6], input_feature[7]);
+            $display(" %b %b %b %b %b %b %b %b", input_feature[8], input_feature[9], input_feature[10], input_feature[11], input_feature[12], input_feature[13], input_feature[14], input_feature[15]);
+            $display(" %b %b %b %b %b %b %b %b", input_feature[16], input_feature[17], input_feature[18], input_feature[19], input_feature[20], input_feature[21], input_feature[22], input_feature[23]);
+            $display(" %b %b %b %b %b %b %b %b", input_feature[24], input_feature[25], input_feature[26], input_feature[27], input_feature[28], input_feature[29], input_feature[30], input_feature[31]);
+            $display(" %b %b %b %b %b %b %b %b", input_feature[32], input_feature[33], input_feature[34], input_feature[35], input_feature[36], input_feature[37], input_feature[38], input_feature[39]);
+            $display(" %b %b %b %b %b %b %b %b", input_feature[40], input_feature[41], input_feature[42], input_feature[43], input_feature[44], input_feature[45], input_feature[46], input_feature[47]);
+            $display(" %b %b %b %b %b %b %b %b", input_feature[48], input_feature[49], input_feature[50], input_feature[51], input_feature[52], input_feature[53], input_feature[54], input_feature[55]);
+            $display(" %b %b %b %b %b %b %b %b", input_feature[56], input_feature[57], input_feature[58], input_feature[59], input_feature[60], input_feature[61], input_feature[62], input_feature[63]);
+            
         end
         else begin
             data_counter <= data_counter + 1;
@@ -64,18 +91,19 @@ end
 always @ (posedge clk) begin
     if (start_conv == 1'b1) begin
         if (cycle == 1) begin
-            if (row < 6) begin // 檢查 row 的範圍
+            if (row < 5) begin // 檢查 row 的範圍
                 row <= row + 1;
             end
             else begin
                 row <= 0;
-                if (line < 6) begin // 檢查 line 的範圍
+                if (line < 5) begin // 檢查 line 的範圍
                     line <= line + 1;
                 end
                 else begin
                     line <= 0;
                     start_conv <= 1'b0;
                     out_st <= 1'b1;
+                    output_data_status <= 1'b1;
                 end
             end
             cycle <= 0;
@@ -104,12 +132,13 @@ end
 
 // Output the result 6x6 matrix
 always @(posedge clk) begin
-    if ( out_st == 1'b1 ) begin
-        dout = conv_result[data_counter] ;
-        data_counter <= data_counter + 1; 
-        if (data_counter == 35) begin
-            data_counter <= 6'b000000; 
-            out_st <= 0;
+    if ( output_data_status == 1'b1 ) begin
+        dout = conv_result[output_counter] ;
+        output_counter <= output_counter + 1;
+        out_st <= 1'b0;
+        if (output_counter == 36) begin // 6x6 matrix
+            output_counter <= 6'b000000;
+            output_data_status <= 1'b0;
         end
     end
 end

code/RAM.v

@@ -16,7 +16,7 @@ always @(posedge clk) begin
     if(~wr) begin //read data
 	    dout <= ram_data[address];
     end
-    else begin 
+    else begin
 	    dout <= 8'd0;
         ram_data[address] <= din;
     end

code/TM.v

@@ -38,11 +38,13 @@ Conv moduleConv(
 /////////////////////////////
 
 
-reg [5:0] write_ram_counter; 
+reg [6:0] write_ram_counter; 
 reg [15:0] conv_result[0:35];
 reg [5:0] output_counter ;
 reg [7:0] fixed_matrix [0:63];
 
+reg output_data_status;
+
 initial begin
     clk = 0;
     in_st = 1'bx; // reset
@@ -124,10 +126,11 @@ initial begin
 
     #(CLK_PERIOD*66)
 
-	in_st <= 1 ;
+	#(CLK_PERIOD) in_st <= 1 ;
+    address <= 6'b000000;
 
-    #(CLK_PERIOD) address <= 6'b000000;
     #(CLK_PERIOD) address <= 6'b000001;
+    in_st <= 1'b0;
     #(CLK_PERIOD) address <= 6'b000010;
     #(CLK_PERIOD) address <= 6'b000011;
     #(CLK_PERIOD) address <= 6'b000100;
@@ -191,28 +194,30 @@ initial begin
     #(CLK_PERIOD) address <= 6'b111110;
     #(CLK_PERIOD) address <= 6'b111111;
 
-	in_st <= 0 ;
-
 
+
     #(CLK_PERIOD*300) $display("finished");
     $stop;
 end
 
 always @(posedge clk) begin
     if ( wr == 1'b1 ) begin
-        address = write_ram_counter; 
-        ram_din = fixed_matrix[write_ram_counter]; 
-        write_ram_counter <= write_ram_counter + 1; 
-        if (write_ram_counter == 63) begin // 8x8 matrix
+        address <= write_ram_counter; 
+        ram_din <= fixed_matrix[write_ram_counter]; 
+        
+        write_ram_counter <= write_ram_counter + 1;
+
+        if (write_ram_counter == 64) begin // 8x8 matrix
 			address <= 6'b000000; 
 			write_ram_counter <= 6'b000000;
 			wr <= 1'b0;
         end
     end	
-	else if ( out_st == 1'b1 ) begin
-        conv_result[output_counter] = dout ;
+
+    else if ( output_data_status == 1'b1 ) begin
+        conv_result[output_counter] <= dout ;
         output_counter <= output_counter + 1; 
-        if (output_counter == 35) begin // 6x6 matrix
+        if (output_counter == 36) begin // 6x6 matrix
             output_counter <= 6'b000000;
             $display("Conv Result:");
             $display("  %b  %b  %b  %b  %b  %b", conv_result[0], conv_result[1], conv_result[2], conv_result[3], conv_result[4], conv_result[5]);
@@ -221,8 +226,13 @@ always @(posedge clk) begin
             $display("  %b  %b  %b  %b  %b  %b", conv_result[18], conv_result[19], conv_result[20], conv_result[21], conv_result[22], conv_result[23]);
             $display("  %b  %b  %b  %b  %b  %b", conv_result[24], conv_result[25], conv_result[26], conv_result[27], conv_result[28], conv_result[29]);
             $display("  %b  %b  %b  %b  %b  %b", conv_result[30], conv_result[31], conv_result[32], conv_result[33], conv_result[34], conv_result[35]);
+            output_data_status = 1'b0;
         end
     end
+
+	else if ( out_st == 1'b1 ) begin
+        output_data_status = 1'b1;
+    end
 end
 
 endmodule