We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
1 parent 086dec0 commit a71a098Copy full SHA for a71a098
libCacheSim/bin/cachesim/main.c
@@ -76,9 +76,7 @@ int main(int argc, char **argv) {
76
"%s %s cache size %8ld%s, %lld req, miss ratio %.4lf",
77
args.reader->trace_path, result[i].cache_name,
78
(long)(result[i].cache_size / size_unit), size_unit_str,
79
- (long long)result[i].n_req,
80
- (double)result[i].n_miss / (double)result[i].n_req,
81
- (double)result[i].n_miss_byte / (double)result[i].n_req_byte);
+ (long long)result[i].n_req, miss_ratio);
82
if (result[i].n_req_byte > result[i].n_req) {
83
snprintf(output_str + strlen(output_str), 1024 - strlen(output_str),
84
", byte miss ratio %.4lf\n", byte_miss_ratio);
0 commit comments