optimize prefetcher readability

Author: zztaki

libCacheSim/cache/cache.c

@@ -153,6 +153,11 @@ cache_obj_t *cache_find_base(cache_t *cache, const request_t *req,
                              const bool update_cache) {
   cache_obj_t *cache_obj = hashtable_find(cache->hashtable, req);
 
+  if (cache->prefetcher && cache->prefetcher->handle_find) {
+    bool hit = (cache_obj != NULL);
+    cache->prefetcher->handle_find(cache, req, hit);
+  }
+
   if (cache_obj != NULL) {
 #ifdef SUPPORT_TTL
     if (cache_obj->exp_time != 0 && cache_obj->exp_time < req->clock_time) {
@@ -199,10 +204,6 @@ bool cache_get_base(cache_t *cache, const request_t *req) {
           cache->cache_name, cache->n_req, req->obj_id, req->obj_size,
           cache->get_occupied_byte(cache), cache->cache_size);
 
-  if (cache->prefetcher && cache->prefetcher->handle_find) {
-    cache->prefetcher->handle_find(cache, req);
-  }
-
   cache_obj_t *obj = cache->find(cache, req, true);
   bool hit = (obj != NULL);
 

libCacheSim/cache/prefetch/Mithril.c

@@ -243,7 +243,8 @@ static void set_Mithril_params(Mithril_params_t *Mithril_params,
  @param req the request containing the request
  @return
 */
-static void Mithril_handle_find(cache_t *cache, const request_t *req) {
+static void Mithril_handle_find(cache_t *cache, const request_t *req,
+                                bool hit) {
   Mithril_params_t *Mithril_params =
       (Mithril_params_t *)(cache->prefetcher->params);
 
@@ -267,7 +268,13 @@ static void Mithril_handle_find(cache_t *cache, const request_t *req) {
     }
   }
 
-  if (Mithril_params->rec_trigger != evict) _Mithril_record_entry(cache, req);
+  // 1. record entry when rec_trigger is each_req.
+  // 2. record entry when (rec_trigger is miss or miss_evict (in other words,
+  // !evict)) && !hit
+  if ((Mithril_params->rec_trigger == each_req) ||
+      (Mithril_params->rec_trigger != evict && !hit)) {
+    _Mithril_record_entry(cache, req);
+  }
 }
 
 /**
@@ -624,13 +631,6 @@ static inline void _Mithril_record_entry(cache_t *cache, const request_t *req) {
 
   int i;
 
-  if (Mithril_params->rec_trigger != each_req &&
-      cache->find(cache, req, false)) {
-    /* if it does not record at each request, check whether it is hit or miss
-     */
-    return;
-  }
-
   /* check it is sequtial or not */
   if (Mithril_params->sequential_type && _Mithril_check_sequential(cache, req))
     return;

libCacheSim/include/libCacheSim/prefetchAlgo.h

@@ -11,7 +11,8 @@ extern "C" {
 struct prefetcher;
 typedef struct prefetcher *(*prefetcher_create_func_ptr)(const char *);
 typedef void (*prefetcher_prefetch_func_ptr)(cache_t *, const request_t *);
-typedef void (*prefetcher_handle_find_func_ptr)(cache_t *, const request_t *);
+typedef void (*prefetcher_handle_find_func_ptr)(cache_t *, const request_t *,
+                                                bool);
 typedef void (*prefetcher_handle_evict_func_ptr)(cache_t *, const request_t *);
 typedef void (*prefetcher_free_func_ptr)(struct prefetcher *);
 typedef struct prefetcher *(*prefetcher_clone_func_ptr)(struct prefetcher *,

test/test_prefetchAlgo.c

@@ -45,9 +45,9 @@ static void print_results(const cache_t *cache, const cache_stat_t *res) {
 }
 
 static void test_Mithril(gconstpointer user_data) {
-  uint64_t miss_cnt_true[] = {79796, 78480, 76126, 75256,
+  uint64_t miss_cnt_true[] = {79999, 78490, 76128, 75257,
                               72336, 72062, 71936, 71667};
-  uint64_t miss_byte_true[] = {3471357440, 3399726080, 3285093888, 3245231616,
+  uint64_t miss_byte_true[] = {3483394560, 3398693888, 3285270016, 3245235712,
                                3092759040, 3077801472, 3075234816, 3061489664};
 
   reader_t *reader = (reader_t *)user_data;