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Fix CI on MacOS (#3813)
* ci macos: lock to rust 1.94.1, use stable clippy Rust 1.95 uses clang 22, clippy nightly is wild * Clippy
1 parent ddf2c39 commit 2a92a83

3 files changed

Lines changed: 16 additions & 11 deletions

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.github/workflows/build_and_test.yml

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@@ -14,6 +14,7 @@ env:
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AFL_PIZZA_MODE: "-1" # this is sad, I know, but it breaks on a certain spring day otherwise :(
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CARGO_TERM_COLOR: always
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CARGO_NET_GIT_FETCH_WITH_CLI: true
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# FIXME: please unpin macos rust stable toolchain once LLVM is bumped to version 22
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MAIN_LLVM_VERSION: 21
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concurrency:
@@ -973,7 +974,7 @@ jobs:
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macos:
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runs-on: macOS-latest
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steps:
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- uses: dtolnay/rust-toolchain@stable
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- uses: dtolnay/rust-toolchain@1.94.1
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with:
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components: clippy
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- name: Install nightly

Justfile

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@@ -130,7 +130,7 @@ clippy:
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# Run clippy on.. some things?
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[macos]
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clippy:
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cargo +nightly clippy --tests --all --exclude libafl_nyx --exclude symcc_runtime --exclude runtime_test
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cargo clippy --tests --all --exclude libafl_nyx --exclude symcc_runtime --exclude runtime_test
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just clippy-excluded
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# Run clippy powershell script

crates/libafl_frida/src/asan/asan_rt.rs

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2666,31 +2666,35 @@ impl AsanRuntime {
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//abuse the fact that the last operand is always the mem operand
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match instr.operands[operands_len - 1] {
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Operand::RegRegOffset(reg1, reg2, size, shift, shift_size) => {
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let ret = Some((
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// let ret =
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Some((
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reg1,
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Some((reg2, size)),
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0,
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instruction_width(&instr),
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Some((shift, shift_size)),
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));
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))
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// log::trace!("Interesting instruction: {}, {:?}", instr.to_string(), ret);
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ret
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// ret
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}
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Operand::RegPreIndex(reg, disp, _) => {
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let ret = Some((reg, None, disp, instruction_width(&instr), None));
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// let ret =
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Some((reg, None, disp, instruction_width(&instr), None))
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// log::trace!("Interesting instruction: {}, {:?}", instr.to_string(), ret);
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ret
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// ret
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}
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Operand::RegPostIndex(reg, _) => {
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//in post index the disp is applied after so it doesn't matter for this memory access
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let ret = Some((reg, None, 0, instruction_width(&instr), None));
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// let ret =
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Some((reg, None, 0, instruction_width(&instr), None))
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// log::trace!("Interesting instruction: {}, {:?}", instr.to_string(), ret);
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ret
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// ret
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}
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Operand::RegPostIndexReg(reg, _) => {
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let ret = Some((reg, None, 0, instruction_width(&instr), None));
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// let ret =
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Some((reg, None, 0, instruction_width(&instr), None))
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// log::trace!("Interesting instruction: {}, {:?}", instr.to_string(), ret);
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ret
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// ret
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}
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_ => None,
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}

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