You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Hand-written, progressively optimized CUDA matrix multiplication — the "Hello World" of HPC. Five kernel variants demonstrate core GPU optimization techniques, from a naive triple loop to **Tensor Core WMMA reaching 40% of cuBLAS throughput**.
|**Naive → Tiled**| Load tiles into shared memory | Data reuse reduces global memory traffic by TILE_SIZE× |
38
+
|**Tiled → Bank-Free**| Pad shared memory `[32][33]`| Eliminates 32-way bank conflicts on column access |
39
+
|**Bank-Free → Double Buffer**| Two shared-memory buffers | Overlaps next-tile load with current-tile compute |
40
+
|**→ Tensor Core**| WMMA API `mma_sync`| Dedicated matrix units, ~8× peak over CUDA cores |
41
+
42
+
## Key Optimization Details
43
+
44
+
**Memory Coalescing** — Naive accesses matrix B columns non-contiguously (stride = N). Tiled loading ensures warp-wide coalesced reads (stride = 1), improving bandwidth utilization from ~12.5% to near 100%.
45
+
46
+
**Shared Memory Tiling** — Each tile is loaded once from global memory and reused TILE_SIZE times in shared memory. Global memory traffic drops from O(N³) to O(N³/TILE_SIZE).
47
+
48
+
**Tensor Core (WMMA)** — A single warp cooperatively executes a 16×16×16 matrix multiply using `nvcuda::wmma` fragments. FP16 inputs with FP32 accumulation provide ~8× peak FLOPS over standard CUDA cores on Ampere.
49
+
50
+
**Roofline Analysis** — SGEMM arithmetic intensity ≈ N/3 for square matrices. Small matrices (N < 256) are memory-bound; large matrices (N > 1024) are compute-bound.
0 commit comments