CoreValidation: fixed failing tests, reworked preprocessed linker scripts

With this fix CoreValidation Cortex-M/A AC6/GCC balanced pass.
Latest CMSIS Toolbox with corrected linker script preprocessing is
needed.

Author: Martin Günther

CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/bootloader.c

@@ -57,6 +57,10 @@ int main(void) {
 
   /* Set non-secure main stack (MSP_NS) */
   __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+
+  /* Set Non-Secure state for Interrupt 0
+    (used in Non-Secure TC_CoreInstr_LoadStoreExclusive Test) */
+  NVIC->ITNS[0] |= 1U;
 
   /* Get non-secure reset handler */
   NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));

CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/gcc_arm.ld

@@ -17,7 +17,7 @@
  */
 
 
-#if defined (__ARM_FEATURE_CMSEx) && (__ARM_FEATURE_CMSEx == 3U)
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 #define __STACKSEAL_SIZE   ( 8 )
 #else
 #define __STACKSEAL_SIZE   ( 0 )
@@ -27,7 +27,7 @@
 #define __HEAP_BASE  ( AlignExpr(+0, 8) )                            /* starts after RW_RAM or RW_NOINIT section, 8 byte aligned */
 
 
-#if defined (__ARM_FEATURE_CMSEx) && (__ARM_FEATURE_CMSEx == 3U)
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 #define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
 #define __CV_SIZE          ( __CMSEVENEER_SIZE )
 #else
@@ -72,7 +72,7 @@ LR_APP __LR_BASE __LR_SIZE  {                                        /* load reg
 #endif
 }
 
-#if defined (__ARM_FEATURE_CMSEx) && (__ARM_FEATURE_CMSEx == 3U)
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {                       /* load/execution region for CMSE Veneers */
   ER_CMSE_VENEER __CV_BASE __CV_SIZE  {
    *(Veneer$$CMSE)

CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct

@@ -17,16 +17,27 @@
  */
 
 
-#if defined (__ARM_FEATURE_CMSEx) && (__ARM_FEATURE_CMSEx == 3U)
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 #define __STACKSEAL_SIZE   ( 8 )
 #else
 #define __STACKSEAL_SIZE   ( 0 )
 #endif
 
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
+#define __CV_SIZE          ( __CMSEVENEER_SIZE )
+#else
+#define __CV_BASE          ( 0xFFFFFFFF )
+#define __CV_SIZE          ( 0 )
+#endif
+
 
 MEMORY
 {
-  ROM   (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  ROM   (rx)  : ORIGIN = __ROM_BASE, LENGTH = ( __ROM_SIZE - __CV_SIZE )
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  CV    (rx)  : ORIGIN = __CV_BASE,  LENGTH = __CV_SIZE
+#endif
   RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
 }
 
@@ -67,6 +78,16 @@ ENTRY(Reset_Handler)
 
 SECTIONS
 {
+  /*
+   * SG veneers:
+   * All SG veneers are placed in the special output section .gnu.sgstubs.
+   */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  .gnu.sgstubs :  {
+    . = ALIGN(32);
+  } > CV
+#endif
+
   .text :
   {
     KEEP(*(.vectors))
@@ -94,16 +115,6 @@ SECTIONS
     KEEP(*(.eh_frame*))
   } > ROM
 
-  /*
-   * SG veneers:
-   * All SG veneers are placed in the special output section .gnu.sgstubs.
-   */
-#if defined (__ARM_FEATURE_CMSEx) && (__ARM_FEATURE_CMSEx == 3U)
-  .gnu.sgstubs :  {
-    . = ALIGN(32);
-  } > ROM
-#endif
-
   .ARM.extab :
   {
     *(.ARM.extab* .gnu.linkonce.armextab.*)