@@ -469,9 +469,9 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
469469 /**
470470 \brief Unsigned Saturate
471471 \details Saturates an unsigned value.
472- \param [in] value Value to be saturated
473- \param [in] sat Bit position to saturate to (0..31)
474- \return Saturated value
472+ \param [in] val Value to be saturated
473+ \param [in] sat Bit position to saturate to (0..31)
474+ \return Saturated value
475475 */
476476 __attribute__((always_inline )) __STATIC_INLINE uint32_t __USAT (int32_t val , uint32_t sat )
477477 {
@@ -493,7 +493,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
493493 (defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
494494 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
495495
496- /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
496+ /** @} end of group CMSIS_Core_InstructionInterface */
497497
498498
499499/* ########################### Core Function Access ########################### */
@@ -516,24 +516,24 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
516516 */
517517/* intrinsic void __disable_irq(void); */
518518
519- #if ((defined (__arm__ ) || \
519+ #if ((defined (__arm__ )) || \
520520 (defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1 )) || \
521521 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1 )) )
522522
523- /**
524- \brief Enable FIQ
525- \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
526- Can only be executed in Privileged modes.
527- */
528- #define __enable_fault_irq __enable_fiq
523+ /**
524+ \brief Enable FIQ
525+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
526+ Can only be executed in Privileged modes.
527+ */
528+ #define __enable_fault_irq __enable_fiq
529529
530530
531- /**
532- \brief Disable FIQ
533- \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
534- Can only be executed in Privileged modes.
535- */
536- #define __disable_fault_irq __disable_fiq
531+ /**
532+ \brief Disable FIQ
533+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
534+ Can only be executed in Privileged modes.
535+ */
536+ #define __disable_fault_irq __disable_fiq
537537
538538#endif /* ( defined (__arm__ ) || \
539539 (defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
@@ -653,6 +653,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
653653
654654 #define __SXTAB16_RORn (ARG1 , ARG2 , ARG3 ) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
655655#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
656- /*@} end of group CMSIS_SIMD_intrinsics */
656+ /** @} end of group CMSIS_SIMD_intrinsics */
657657
658658#endif /* __CMSIS_ARMCC_H */
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