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JonatanAntoniJonatanAntoni
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Run Core tests with IAR toolchain
1 parent b7f79bb commit c25fd1e

10 files changed

Lines changed: 88 additions & 26 deletions

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‎.github/workflows/core.yml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ jobs:
2020

2121
env:
2222
ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }}
23+
IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }}
2324

2425
steps:
2526
- uses: actions/checkout@v4

‎CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -206,8 +206,7 @@ __iar_builtin_ISB();
206206
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
207207

208208
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
209-
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
210-
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
209+
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
211210
// without main extensions, the non-secure PSPLIM is RAZ/WI
212211
#define __TZ_get_PSPLIM_NS() (0U)
213212
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))

‎CMSIS/Core/Test/build.py‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -82,11 +82,6 @@ def run_lit(toolchain, device, optimize):
8282
return ["lit", "--xunit-xml-output", f"lit.xml", "-D", f"toolchain={toolchain}", "-D", f"device={device}", "-D", f"optimize={optimize}", "src" ]
8383

8484

85-
@matrix_filter
86-
def filter_iar(config):
87-
return config.compiler == CompilerAxis.IAR
88-
89-
9085
@matrix_filter
9186
def filter_gcc_cm52(config):
9287
device = config.device.match('CM52*')

‎CMSIS/Core/Test/lit.cfg.py‎

Lines changed: 55 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@
117117
'triple': 'thumbv7-em',
118118
'abi': 'eabi',
119119
'mcpu': 'cortex-m7',
120-
'mfpu': 'fpv4-sp-d16',
120+
'mfpu': 'fpv5-sp-d16',
121121
'mpu': True,
122122
'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
123123
'header': 'core_cm7.h',
@@ -847,13 +847,63 @@ def get_ccflags(self):
847847

848848
return ccflags
849849

850+
class Toolchain_IAR(Toolchain):
851+
OPTIMIZE = {
852+
'none': '-On',
853+
'balanced': '-Oh',
854+
'speed': '-Ohs',
855+
'size': '-Ohz'
856+
}
857+
FPU = {
858+
'none': 'none',
859+
'fpv4-sp-d16': 'VFPv4-SP',
860+
'fpv5-sp-d16': 'VFPv5-SP',
861+
'fpv5-d16': 'VFPv5_D16',
862+
'neon-vfpv3': 'VFPv3',
863+
'neon-vfpv4': 'VFPv4',
864+
}
865+
CPU = {
866+
'CA5': 'Cortex-A5',
867+
'CA5neon': 'Cortex-A5.neon',
868+
'CA7': 'Cortex-A7.no_neon',
869+
'CA7neon': 'Cortex-A7',
870+
'CA9': 'Cortex-A9.no_neon',
871+
'CA9neon': 'Cortex-A9',
872+
}
873+
def __init__(self, **args):
874+
super().__init__('IAR', **args)
875+
876+
def get_cc(self):
877+
return os.path.join(self.get_root(), 'iccarm')
878+
879+
def cpu(self):
880+
if self.device in self.CPU:
881+
return self.CPU[self.device]
882+
return DEVICES[self.device]["mcpu"]
883+
884+
def fpu(self):
885+
return self.FPU[DEVICES[self.device]["mfpu"]]
886+
887+
def get_ccflags(self):
888+
ccflags = [
889+
self.OPTIMIZE[self.optimize],
890+
f'--cpu={self.cpu()}', f'--fpu={self.fpu()}',
891+
'-I', os.path.abspath('../Include'), '-c', '-D', f'CORE_HEADER="{DEVICES[device]["header"]}"']
892+
if device.endswith('S') and not device.endswith('NS'):
893+
ccflags += ["--cmse"]
894+
ccflags += list(sum([('-D', f'{define}={value}') for (define, value) in DEVICES[self.device]['defines'].items()], ()))
895+
896+
return ccflags
897+
850898
tc = None
851899
if toolchain == 'AC6':
852900
tc = Toolchain_AC6(device=device, optimize=optimize)
853901
elif toolchain == 'GCC':
854902
tc = Toolchain_GCC(device=device, optimize=optimize)
855903
elif toolchain == 'Clang':
856904
tc = Toolchain_Clang(device=device, optimize=optimize)
905+
elif toolchain == 'IAR':
906+
tc = Toolchain_IAR(device=device, optimize=optimize)
857907

858908
prefixes = ['CHECK']
859909
if device.endswith('NS'):
@@ -864,6 +914,10 @@ def get_ccflags(self):
864914
prefixes += ['CHECK-THUMB']
865915
elif DEVICES[device]['arch'].startswith('arm'):
866916
prefixes += ['CHECK-ARM']
917+
if toolchain == 'IAR':
918+
prefixes += ['CHECK-IAR']
919+
else:
920+
prefixes += ['CHECK-NON-IAR']
867921

868922
if DEVICES[device]["mfpu"] != 'none':
869923
config.available_features.add('fpu')

‎CMSIS/Core/Test/src/cpsr.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ void set_cpsr() {
2222
void get_mode() {
2323
// CHECK-LABEL: <get_mode>:
2424
// CHECK: mrs [[REG:r[0-9]+]], apsr
25-
// CHECK: and [[REG]], [[REG]], #{{31|0x1f}}
25+
// CHECK: and{{s?}} [[REG]], [[REG]], #{{31|0x1f}}
2626
volatile uint32_t result = __get_mode();
2727
// CHECK: {{(bx lr)|(pop {.*pc})}}
2828
}

‎CMSIS/Core/Test/src/noreturn.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ static void func() {
99

1010
void noreturn() {
1111
// CHECK-LABEL: <noreturn>:
12-
// CHECK: b 0x0 <noreturn>
12+
// CHECK: {{b|bl}} {{0x[0-9a-fA-F]+}} <noreturn{{.*}}>
1313
func();
1414
// CHECK-NOT: bx lr
1515
}

‎CMSIS/Core/Test/src/ror.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@ static volatile uint32_t b = 2u;
77

88
void ror() {
99
// CHECK-LABEL: <ror>:
10-
// CHECK-THUMB: ror{{ne|s|.w}} {{r[0-9]+}}, {{r[0-9]+}}
11-
// CHECK-ARM: {{ror|rorne}} {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
10+
// CHECK-THUMB: ror{{ne|s|.w|s.w}} {{r[0-9]+}}, {{r[0-9]+}}
11+
// CHECK-ARM: ror{{s?|ne}} {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
1212
volatile uint32_t c = __ROR(a, b);
1313
// CHECK: {{(bx lr)|(pop {.*pc})}}
1414
}

‎CMSIS/Core/Test/src/rrx.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ static volatile uint32_t a = 10u;
77

88
void rrx() {
99
// CHECK-LABEL: <rrx>:
10-
// CHECK: rrx {{r[0-9]+}}, {{r[0-9]+}}
10+
// CHECK: {{rrx|rrxs}} {{r[0-9]+}}, {{r[0-9]+}}
1111
volatile uint32_t c = __RRX(a);
1212
// CHECK: {{(bx lr)|(pop {.*pc})}}
1313
}

‎CMSIS/Core/Test/src/simd.c‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -471,23 +471,29 @@ void pkhtb() {
471471

472472
void sxtb16_ror() {
473473
// CHECK-LABEL: <sxtb16_ror>:
474-
// CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #8
474+
// CHECK-NON-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #8
475+
// CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#8|#0x8}}
476+
// CHECK-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
475477
volatile uint32_t result = __SXTB16_RORn(s32_1, 8);
476478

477-
// CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #16
479+
// CHECK-NON-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #16
480+
// CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#16|#0x10}}
481+
// CHECK-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
478482
result = __SXTB16_RORn(s32_1, 16);
479483

480-
// CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #24
484+
// CHECK-NON-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #24
485+
// CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#24|#0x18}}
486+
// CHECK-IAR: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
481487
result = __SXTB16_RORn(s32_1, 24);
482488

483-
// CHECK-THUMB: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
484-
// CHECK-ARM: ror [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
489+
// CHECK-THUMB: ror{{s?}}.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
490+
// CHECK-ARM: ror{{s?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
485491
// CHECK: sxtb16 {{r[0-9]+}}, [[REG]]
486492
// CHECK-NOT: , ror
487493
result = __SXTB16_RORn(s32_1, 5);
488494

489495
// CHECK-THUMB: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}}
490-
// CHECK-ARM: ror{{(ne)?}} {{r[0-9]+}}, {{r[0-9]+}}
496+
// CHECK-ARM: ror{{s?|ne}} {{r[0-9]+}}, {{r[0-9]+}}
491497
// CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
492498
// CHECK-NOT: , ror
493499
result = __SXTB16_RORn(s32_1, u8);
@@ -498,23 +504,29 @@ void sxtb16_ror() {
498504
void sxtab16_ror() {
499505
// CHECK-LABEL: <sxtab16_ror>:
500506

501-
// CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #8
507+
// CHECK-NON-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #8
508+
// CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#8|#0x8}}
509+
// CHECK-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}
502510
volatile uint32_t result = __SXTAB16_RORn(s32_1, s32_2, 8);
503511

504-
// CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #16
512+
// CHECK-NON-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #16
513+
// CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#16|#0x10}}
514+
// CHECK-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}
505515
result = __SXTAB16_RORn(s32_1, s32_2, 16);
506516

507-
// CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #24
517+
// CHECK-NON-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #24
518+
// CHECK-IAR: rors{{(\.w)?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#24|#0x18}}
519+
// CHECK-IAR: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}
508520
result = __SXTAB16_RORn(s32_1, s32_2, 24);
509521

510-
// CHECK-THUMB: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
511-
// CHECK-ARM: ror [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
522+
// CHECK-THUMB: ror{{s?}}.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
523+
// CHECK-ARM: ror{{s?}} [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
512524
// CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, [[REG]]
513525
// CHECK-NOT: , ror
514526
result = __SXTAB16_RORn(s32_1, s32_2, 5);
515527

516528
// CHECK-THUMB: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}}
517-
// CHECK-ARM: ror{{(ne)?}} {{r[0-9]+}}, {{r[0-9]+}}
529+
// CHECK-ARM: ror{{s?|ne}} {{r[0-9]+}}, {{r[0-9]+}}
518530
// CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
519531
// CHECK-NOT: , ror
520532
result = __SXTAB16_RORn(s32_1, s32_2, u8);

‎CMSIS/Core/Test/vcpkg-configuration.json‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
"requires": {
1010
"arm:compilers/arm/armclang": "6.23.0",
1111
"arm:compilers/arm/arm-none-eabi-gcc": "14.2.1",
12-
"arm:compilers/arm/llvm-embedded": "19.1.5"
12+
"arm:compilers/arm/llvm-embedded": "19.1.5",
13+
"arm:compilers/iar/cxarm": "9.60.4"
1314
}
1415
}

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