Core: Clean up header files

Author: GuentherMartin

CMSIS/Core/Include/a-profile/cmsis_armclang_a.h

@@ -1,9 +1,3 @@
-/**************************************************************************//**
- * @file     cmsis_armclang_a.h
- * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V1.2.3
- * @date     11. October 2023
- ******************************************************************************/
 /*
  * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
  *
@@ -22,6 +16,10 @@
  * limitations under the License.
  */
 
+/*
+ * CMSIS-Core(A) Compiler ARMClang (Arm Compiler 6) Header File
+ */
+
 #ifndef __CMSIS_ARMCLANG_A_H
 #define __CMSIS_ARMCLANG_A_H
 
@@ -102,13 +100,15 @@
   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 #endif
 
+
 /* ##########################  Core Instruction Access  ######################### */
 /**
   \brief   No Operation
   \details No Operation does nothing. This instruction can be used for code alignment purposes.
  */
 #define __NOP                             __builtin_arm_nop
 
+
 /**
   \brief   Wait For Interrupt
   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
@@ -218,6 +218,7 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
  */
 #define __RBIT          __builtin_arm_rbit
 
+
 /**
   \brief   Count leading zeros
   \details Counts the number of leading zeros of a data value.
@@ -242,6 +243,7 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
   return __builtin_clz(value);
 }
 
+
 /**
   \brief   LDR Exclusive (8 bit)
   \details Executes a exclusive LDR instruction for 8 bit value.
@@ -502,7 +504,7 @@ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
   int32_t result;
 
   __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-  return(result);
+  return (result);
 }
 
 #endif /* (__ARM_FEATURE_DSP == 1) */
@@ -707,23 +709,23 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
 __STATIC_INLINE void __FPU_Enable(void)
 {
   __ASM volatile(
-    //Permit access to VFP/NEON, registers by modifying CPACR
+    // Permit access to VFP/NEON, registers by modifying CPACR
     "        MRC     p15,0,R1,c1,c0,2  \n"
     "        ORR     R1,R1,#0x00F00000 \n"
     "        MCR     p15,0,R1,c1,c0,2  \n"
 
-    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    // Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
     "        ISB                       \n"
 
-    //Enable VFP/NEON
+    // Enable VFP/NEON
     "        VMRS    R1,FPEXC          \n"
     "        ORR     R1,R1,#0x40000000 \n"
     "        VMSR    FPEXC,R1          \n"
 
-    //Initialise VFP/NEON registers to 0
+    // Initialise VFP/NEON registers to 0
     "        MOV     R2,#0             \n"
 
-    //Initialise D16 registers to 0
+    // Initialise D16 registers to 0
     "        VMOV    D0, R2,R2         \n"
     "        VMOV    D1, R2,R2         \n"
     "        VMOV    D2, R2,R2         \n"
@@ -742,7 +744,7 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D15,R2,R2         \n"
 
 #if (defined(__ARM_NEON) && (__ARM_NEON == 1))
-    //Initialise D32 registers to 0
+    // Initialise D32 registers to 0
     "        VMOV    D16,R2,R2         \n"
     "        VMOV    D17,R2,R2         \n"
     "        VMOV    D18,R2,R2         \n"
@@ -761,7 +763,7 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D31,R2,R2         \n"
 #endif
 
-    //Initialise FPSCR to a known state
+  // Initialise FPSCR to a known state
     "        VMRS    R1,FPSCR          \n"
     "        LDR     R2,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
     "        AND     R1,R1,R2          \n"

CMSIS/Core/Include/a-profile/cmsis_clang_a.h

@@ -1,9 +1,3 @@
-/**************************************************************************//**
- * @file     cmsis_clang_a.h
- * @brief    CMSIS compiler Clang header file
- * @version  V0.1.0
- * @date     24. October 2023
- ******************************************************************************/
 /*
  * Copyright (c) 2023 Arm Limited. All rights reserved.
  *
@@ -22,6 +16,10 @@
  * limitations under the License.
  */
 
+/*
+ * CMSIS-Core(A) Compiler LLVM/Clang Header File
+ */
+
 #ifndef __CMSIS_CLANG_A_H
 #define __CMSIS_CLANG_A_H
 
@@ -113,6 +111,7 @@
  */
 #define __NOP()                             __ASM volatile ("nop")
 
+
 /**
   \brief   Wait For Interrupt
   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
@@ -285,6 +284,7 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
   return __builtin_clz(value);
 }
 
+
 /**
   \brief   LDR Exclusive (8 bit)
   \details Executes a exclusive LDR instruction for 8 bit value.
@@ -600,7 +600,8 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 
 /* ###################  Compiler specific Intrinsics  ########################### */
 
-#if (__ARM_FEATURE_DSP == 1)
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
 #define     __SADD8                 __builtin_arm_sadd8
 #define     __QADD8                 __builtin_arm_qadd8
 #define     __SHADD8                __builtin_arm_shadd8

CMSIS/Core/Include/a-profile/cmsis_cp15.h

@@ -1,9 +1,3 @@
-/**************************************************************************//**
- * @file     cmsis_cp15.h
- * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.2
- * @date     19. December 2022
- ******************************************************************************/
 /*
  * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
  *
@@ -22,13 +16,17 @@
  * limitations under the License.
  */
 
+/*
+ * CMSIS-Core(A) Compiler Specific Macros, Functions, Instructions
+ */
+
 #ifndef __CMSIS_CP15_H
 #define __CMSIS_CP15_H
 
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
+  #pragma clang system_header    /* treat file as system include file */
 #endif
 
 /** \brief  Get ACTLR

CMSIS/Core/Include/a-profile/cmsis_gcc_a.h

@@ -1,9 +1,3 @@
-/**************************************************************************//**
- * @file     cmsis_gcc_a.h
- * @brief    CMSIS compiler GCC header file
- * @version  V1.3.4
- * @date     11. October 2023
- ******************************************************************************/
 /*
  * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
  *
@@ -22,6 +16,10 @@
  * limitations under the License.
  */
 
+/*
+ * CMSIS-Core(A) Compiler GCC Header File
+ */
+
 #ifndef __CMSIS_GCC_A_H
 #define __CMSIS_GCC_A_H
 
@@ -120,6 +118,7 @@
  */
 #define __NOP()                             __ASM volatile ("nop")
 
+
 /**
   \brief   Wait For Interrupt
   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
@@ -294,6 +293,7 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
   return __builtin_clz(value);
 }
 
+
 /**
   \brief   LDR Exclusive (8 bit)
   \details Executes a exclusive LDR instruction for 8 bit value.
@@ -623,7 +623,8 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 
 /* ###################  Compiler specific Intrinsics  ########################### */
 
-#if (__ARM_FEATURE_DSP == 1)
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
 #define     __SADD8                 __builtin_arm_sadd8
 #define     __QADD8                 __builtin_arm_qadd8
 #define     __SHADD8                __builtin_arm_shadd8

CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h

@@ -1,30 +1,25 @@
-/**************************************************************************//**
- * @file     cmsis_iccarm_a.h
- * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.0.8
- * @date     13. November 2022
- ******************************************************************************/
-
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2017-2018 IAR Systems
-// Copyright (c) 2018-2019 Arm Limited 
-//
-// SPDX-License-Identifier: Apache-2.0
-//
-// Licensed under the Apache License, Version 2.0 (the "License")
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-//------------------------------------------------------------------------------
+/*
+ * Copyright (c) 2017-2018 IAR Systems
+ * Copyright (c) 2018-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
 
+/*
+ * CMSIS-Core(A) Compiler ICCARM (IAR Compiler for Arm) Header File
+ */
 
 #ifndef __CMSIS_ICCARM_A_H__
 #define __CMSIS_ICCARM_A_H__
@@ -185,16 +180,6 @@
   #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
 #endif
 
-#if 0
-#ifndef __UNALIGNED_UINT32   /* deprecated */
-  #pragma language=save
-  #pragma language=extended
-  __packed struct  __iar_u32 { uint32_t v; };
-  #pragma language=restore
-  #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
-#endif
-#endif
-
 #ifndef   __USED
   #if __ICCARM_V8
     #define __USED __attribute__((used))

CMSIS/Core/Include/a-profile/irq_ctrl.h

@@ -1,9 +1,3 @@
-/**************************************************************************//**
- * @file     irq_ctrl.h
- * @brief    Interrupt Controller API header file
- * @version  V1.1.0
- * @date     03. March 2020
- ******************************************************************************/
 /*
  * Copyright (c) 2017-2020 ARM Limited. All rights reserved.
  *
@@ -22,13 +16,17 @@
  * limitations under the License.
  */
 
+/*
+ * CMSIS-Core(A) Interrupt Controller API Header File
+ */
+
 #ifndef IRQ_CTRL_H_
 #define IRQ_CTRL_H_
 
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
+  #pragma clang system_header    /* treat file as system include file */
 #endif
 
 #include <stdint.h>

CMSIS/Core/Include/cmsis_compiler.h

@@ -1,9 +1,3 @@
-/**************************************************************************//**
- * @file     cmsis_compiler.h
- * @brief    CMSIS compiler generic header file
- * @version  V6.0.0
- * @date     23. November 2023
- ******************************************************************************/
 /*
  * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
  *
@@ -22,6 +16,10 @@
  * limitations under the License.
  */
 
+/*
+ * CMSIS Compiler Generic Header File
+ */
+
 #ifndef __CMSIS_COMPILER_H
 #define __CMSIS_COMPILER_H
 
@@ -137,10 +135,6 @@
   #ifndef   __PACKED_UNION
     #define __PACKED_UNION                         union __attribute__((packed))
   #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
   #ifndef   __UNALIGNED_UINT16_WRITE
     __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
     #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
@@ -214,10 +208,6 @@
   #ifndef   __PACKED_UNION
     #define __PACKED_UNION                         union __packed__
   #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __packed__ T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
   #ifndef   __UNALIGNED_UINT16_WRITE
     __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
     #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
@@ -290,10 +280,6 @@
   #ifndef   __PACKED_UNION
     #define __PACKED_UNION                         @packed union
   #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    @packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
   #ifndef   __UNALIGNED_UINT16_WRITE
     __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
     #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))

CMSIS/Core/Include/cmsis_version.h

@@ -17,7 +17,7 @@
  */
 
 /*
- * CMSIS Core Version definitions
+ * CMSIS Core Version Definitions
  */
 
 #if   defined ( __ICCARM__ )