Skip to content

Commit dd2c27b

Browse files
Masmiseim36Masmiseim36
committed
- Add initial support for ARMv8A, ARMV7R and ARMV8R
- Added core_cxx.h files for ARMv8A, ARMV7R and ARMV8R based profiles - Moved gic peripheral to separate file - Moved __FPU_Enable function to the architecture specific file
1 parent 03d57c8 commit dd2c27b

27 files changed

Lines changed: 3035 additions & 950 deletions

CMSIS/Core/Include/core_ca.h renamed to CMSIS/Core/Include/a-profile/armv7a.h

Lines changed: 76 additions & 736 deletions
Large diffs are not rendered by default.

CMSIS/Core/Include/a-profile/cmsis_cp15.h renamed to CMSIS/Core/Include/a-profile/armv7a_cp15.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -362,10 +362,10 @@ __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
362362

363363
/******************************* VIRTUAL TIMER *******************************/
364364
/** see [ARM DDI 0406C.d] :
365-
. §B4.1.31 "CNTV_CTL, Counter-timer Virtual Timer Control register"
366-
. §B4.1.32 "CNTV_CVAL, Counter-timer Virtual Timer CompareValue register"
367-
. §B4.1.33 "CNTV_TVAL, Counter-timer Virtual Timer TimerValue register"
368-
. §B4.1.34 "CNTVCT, Counter-timer Virtual Count register"
365+
* B4.1.31 "CNTV_CTL, Counter-timer Virtual Timer Control register"
366+
* B4.1.32 "CNTV_CVAL, Counter-timer Virtual Timer CompareValue register"
367+
* B4.1.33 "CNTV_TVAL, Counter-timer Virtual Timer TimerValue register"
368+
* B4.1.34 "CNTVCT, Counter-timer Virtual Count register"
369369
**/
370370
/** \brief Set CNTV_TVAL
371371
This function assigns the given value to VL1 Virtual Timer Value Register (CNTV_TVAL).

‎CMSIS/Core/Include/a-profile/armv8a.h‎

Lines changed: 647 additions & 0 deletions
Large diffs are not rendered by default.

‎CMSIS/Core/Include/a-profile/armv8a_cp15.h‎

Lines changed: 143 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,143 @@
1+
/**************************************************************************//**
2+
* @file armv8a_cp15.h
3+
* @brief CMSIS compiler specific macros, functions, instructions
4+
* @version V6.0.0
5+
* @date 4. August 2023
6+
******************************************************************************/
7+
/*
8+
* Copyright (c) 2009-2023 ARM Limited. All rights reserved.
9+
*
10+
* SPDX-License-Identifier: Apache-2.0
11+
*
12+
* Licensed under the Apache License, Version 2.0 (the License); you may
13+
* not use this file except in compliance with the License.
14+
* You may obtain a copy of the License at
15+
*
16+
* www.apache.org/licenses/LICENSE-2.0
17+
*
18+
* Unless required by applicable law or agreed to in writing, software
19+
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
20+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21+
* See the License for the specific language governing permissions and
22+
* limitations under the License.
23+
*/
24+
#include <stdint.h>
25+
26+
#if defined ( __ICCARM__ )
27+
#pragma system_include /* treat file as system include file for MISRA check */
28+
#elif defined (__clang__)
29+
#pragma clang system_header /* treat file as system include file */
30+
#endif
31+
32+
#ifndef __CMSIS_SYSTEM_CONTROL_H
33+
#define __CMSIS_SYSTEM_CONTROL_H
34+
35+
36+
/** \brief Get MPIDR EL1
37+
\return Multiprocessor Affinity Register value
38+
*/
39+
__STATIC_FORCEINLINE uint64_t __get_MPIDR_EL1(void)
40+
{
41+
uint64_t result;
42+
__ASM volatile("MRS %0, MPIDR_EL1" : "=r" (result) : : "memory");
43+
return result;
44+
}
45+
46+
/** \brief Get MAIR EL3
47+
\return MAIR value
48+
*/
49+
__STATIC_FORCEINLINE uint64_t __get_MAIR_EL3(void)
50+
{
51+
uint64_t result;
52+
__ASM volatile("MRS %0, mair_el3" : "=r" (result) : : "memory");
53+
return result;
54+
}
55+
56+
/** \brief Set MAIR EL3
57+
\param [in] mair MAIR value to set
58+
*/
59+
__STATIC_FORCEINLINE void __set_MAIR_EL3(uint64_t mair)
60+
{
61+
__ASM volatile("MSR mair_el3, %0" : : "r" (mair) : "memory");
62+
}
63+
64+
/** \brief Get TCR EL3
65+
\return TCR value
66+
*/
67+
__STATIC_FORCEINLINE uint64_t __get_TCR_EL3(void)
68+
{
69+
uint64_t result;
70+
__ASM volatile("MRS %0, tcr_el3" : "=r" (result) : : "memory");
71+
return result;
72+
}
73+
74+
/** \brief Set TCR EL3
75+
\param [in] tcr TCR value to set
76+
*/
77+
__STATIC_FORCEINLINE void __set_TCR_EL3(uint64_t tcr)
78+
{
79+
__ASM volatile("MSR tcr_el3, %0" : : "r" (tcr) : "memory");
80+
}
81+
82+
/** \brief Get TTBR0 EL3
83+
\return Translation Table Base Register 0 value
84+
*/
85+
__STATIC_FORCEINLINE uint64_t __get_TTBR0_EL3(void)
86+
{
87+
uint64_t result;
88+
__ASM volatile("MRS %0, ttbr0_el3" : "=r" (result) : : "memory");
89+
return result;
90+
}
91+
92+
/** \brief Set TTBR0 EL3
93+
\param [in] ttbr0 Translation Table Base Register 0 value to set
94+
*/
95+
__STATIC_FORCEINLINE void __set_TTBR0_EL3(uint64_t ttbr0)
96+
{
97+
__ASM volatile("MSR ttbr0_el3, %0" : : "r" (ttbr0) : "memory");
98+
}
99+
100+
/** \brief Get SCTLR EL3
101+
\return STRLR EL3 value
102+
*/
103+
__STATIC_FORCEINLINE uint64_t __get_SCTLR_EL3(void)
104+
{
105+
uint64_t result;
106+
__ASM volatile("MRS %0, sctlr_el3" : "=r" (result) : : "memory");
107+
return result;
108+
}
109+
110+
/** \brief Set SCTLR EL3
111+
\param [in] vbar SCTLR value to set
112+
*/
113+
__STATIC_FORCEINLINE void __set_SCTLR_EL3(uint64_t sctlr)
114+
{
115+
__ASM volatile("MSR sctlr_el3, %0" : : "r" (sctlr) : "memory");
116+
}
117+
118+
/** \brief Set VBAR EL3
119+
\param [in] vbar VBAR value to set
120+
*/
121+
__STATIC_FORCEINLINE void __set_VBAR_EL3(uint64_t vbar)
122+
{
123+
__ASM volatile("MSR vbar_el3, %0" : : "r" (vbar) : "memory");
124+
}
125+
126+
/** \brief Set VBAR EL2
127+
\param [in] vbar VBAR value to set
128+
*/
129+
__STATIC_FORCEINLINE void __set_VBAR_EL2(uint64_t vbar)
130+
{
131+
__ASM volatile("MSR vbar_el2, %0" : : "r" (vbar) : "memory");
132+
}
133+
134+
/** \brief Set VBAR EL1
135+
\param [in] vbar VBAR value to set
136+
*/
137+
__STATIC_FORCEINLINE void __set_VBAR_EL1(uint64_t vbar)
138+
{
139+
__ASM volatile("MSR vbar_el1, %0" : : "r" (vbar) : "memory");
140+
}
141+
142+
143+
#endif /* __CMSIS_SYSTEM_CONTROL_H */

‎CMSIS/Core/Include/a-profile/cmsis_armclang_a.h‎

Lines changed: 0 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -700,76 +700,4 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
700700
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
701701
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
702702

703-
#include "cmsis_cp15.h"
704-
705-
/** \brief Enable Floating Point Unit
706-
707-
Critical section, called from undef handler, so systick is disabled
708-
*/
709-
__STATIC_INLINE void __FPU_Enable(void)
710-
{
711-
__ASM volatile(
712-
// Permit access to VFP/NEON, registers by modifying CPACR
713-
" MRC p15,0,R1,c1,c0,2 \n"
714-
" ORR R1,R1,#0x00F00000 \n"
715-
" MCR p15,0,R1,c1,c0,2 \n"
716-
717-
// Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
718-
" ISB \n"
719-
720-
// Enable VFP/NEON
721-
" VMRS R1,FPEXC \n"
722-
" ORR R1,R1,#0x40000000 \n"
723-
" VMSR FPEXC,R1 \n"
724-
725-
// Initialise VFP/NEON registers to 0
726-
" MOV R2,#0 \n"
727-
728-
// Initialise D16 registers to 0
729-
" VMOV D0, R2,R2 \n"
730-
" VMOV D1, R2,R2 \n"
731-
" VMOV D2, R2,R2 \n"
732-
" VMOV D3, R2,R2 \n"
733-
" VMOV D4, R2,R2 \n"
734-
" VMOV D5, R2,R2 \n"
735-
" VMOV D6, R2,R2 \n"
736-
" VMOV D7, R2,R2 \n"
737-
" VMOV D8, R2,R2 \n"
738-
" VMOV D9, R2,R2 \n"
739-
" VMOV D10,R2,R2 \n"
740-
" VMOV D11,R2,R2 \n"
741-
" VMOV D12,R2,R2 \n"
742-
" VMOV D13,R2,R2 \n"
743-
" VMOV D14,R2,R2 \n"
744-
" VMOV D15,R2,R2 \n"
745-
746-
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
747-
// Initialise D32 registers to 0
748-
" VMOV D16,R2,R2 \n"
749-
" VMOV D17,R2,R2 \n"
750-
" VMOV D18,R2,R2 \n"
751-
" VMOV D19,R2,R2 \n"
752-
" VMOV D20,R2,R2 \n"
753-
" VMOV D21,R2,R2 \n"
754-
" VMOV D22,R2,R2 \n"
755-
" VMOV D23,R2,R2 \n"
756-
" VMOV D24,R2,R2 \n"
757-
" VMOV D25,R2,R2 \n"
758-
" VMOV D26,R2,R2 \n"
759-
" VMOV D27,R2,R2 \n"
760-
" VMOV D28,R2,R2 \n"
761-
" VMOV D29,R2,R2 \n"
762-
" VMOV D30,R2,R2 \n"
763-
" VMOV D31,R2,R2 \n"
764-
#endif
765-
766-
// Initialise FPSCR to a known state
767-
" VMRS R1,FPSCR \n"
768-
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
769-
" AND R1,R1,R2 \n"
770-
" VMSR FPSCR,R1 "
771-
: : : "cc", "r1", "r2"
772-
);
773-
}
774-
775703
#endif /* __CMSIS_ARMCLANG_A_H */

‎CMSIS/Core/Include/a-profile/cmsis_gcc_a.h‎

Lines changed: 0 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -863,72 +863,6 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
863863
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
864864
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
865865

866-
#include "cmsis_cp15.h"
867-
868-
/** \brief Enable Floating Point Unit
869-
870-
Critical section, called from undef handler, so systick is disabled
871-
*/
872-
__STATIC_INLINE void __FPU_Enable(void)
873-
{
874-
// Permit access to VFP/NEON, registers by modifying CPACR
875-
const uint32_t cpacr = __get_CPACR();
876-
__set_CPACR(cpacr | 0x00F00000ul);
877-
__ISB();
878-
879-
// Enable VFP/NEON
880-
const uint32_t fpexc = __get_FPEXC();
881-
__set_FPEXC(fpexc | 0x40000000ul);
882-
883-
__ASM volatile(
884-
// Initialise VFP/NEON registers to 0
885-
" MOV R2,#0 \n"
886-
887-
// Initialise D16 registers to 0
888-
" VMOV D0, R2,R2 \n"
889-
" VMOV D1, R2,R2 \n"
890-
" VMOV D2, R2,R2 \n"
891-
" VMOV D3, R2,R2 \n"
892-
" VMOV D4, R2,R2 \n"
893-
" VMOV D5, R2,R2 \n"
894-
" VMOV D6, R2,R2 \n"
895-
" VMOV D7, R2,R2 \n"
896-
" VMOV D8, R2,R2 \n"
897-
" VMOV D9, R2,R2 \n"
898-
" VMOV D10,R2,R2 \n"
899-
" VMOV D11,R2,R2 \n"
900-
" VMOV D12,R2,R2 \n"
901-
" VMOV D13,R2,R2 \n"
902-
" VMOV D14,R2,R2 \n"
903-
" VMOV D15,R2,R2 \n"
904-
905-
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
906-
// Initialise D32 registers to 0
907-
" VMOV D16,R2,R2 \n"
908-
" VMOV D17,R2,R2 \n"
909-
" VMOV D18,R2,R2 \n"
910-
" VMOV D19,R2,R2 \n"
911-
" VMOV D20,R2,R2 \n"
912-
" VMOV D21,R2,R2 \n"
913-
" VMOV D22,R2,R2 \n"
914-
" VMOV D23,R2,R2 \n"
915-
" VMOV D24,R2,R2 \n"
916-
" VMOV D25,R2,R2 \n"
917-
" VMOV D26,R2,R2 \n"
918-
" VMOV D27,R2,R2 \n"
919-
" VMOV D28,R2,R2 \n"
920-
" VMOV D29,R2,R2 \n"
921-
" VMOV D30,R2,R2 \n"
922-
" VMOV D31,R2,R2 \n"
923-
#endif
924-
: : : "cc", "r2"
925-
);
926-
927-
// Initialise FPSCR to a known state
928-
const uint32_t fpscr = __get_FPSCR();
929-
__set_FPSCR(fpscr & 0x00086060ul);
930-
}
931-
932866
/*@} end of group CMSIS_Core_intrinsics */
933867

934868
#pragma GCC diagnostic pop

‎CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h‎

Lines changed: 0 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -258,8 +258,6 @@
258258
#define __set_CP64(cp, op1, Rt, CRm) \
259259
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
260260

261-
#include "cmsis_cp15.h"
262-
263261
#define __NOP __iar_builtin_no_operation
264262

265263
#define __CLZ __iar_builtin_CLZ
@@ -480,75 +478,6 @@ __IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
480478

481479
#define __get_mode() (__get_CPSR() & 0x1FU)
482480

483-
__STATIC_INLINE
484-
void __FPU_Enable(void)
485-
{
486-
__ASM volatile(
487-
//Permit access to VFP/NEON, registers by modifying CPACR
488-
" MRC p15,0,R1,c1,c0,2 \n"
489-
" ORR R1,R1,#0x00F00000 \n"
490-
" MCR p15,0,R1,c1,c0,2 \n"
491-
492-
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
493-
" ISB \n"
494-
495-
//Enable VFP/NEON
496-
" VMRS R1,FPEXC \n"
497-
" ORR R1,R1,#0x40000000 \n"
498-
" VMSR FPEXC,R1 \n"
499-
500-
//Initialise VFP/NEON registers to 0
501-
" MOV R2,#0 \n"
502-
503-
//Initialise D16 registers to 0
504-
" VMOV D0, R2,R2 \n"
505-
" VMOV D1, R2,R2 \n"
506-
" VMOV D2, R2,R2 \n"
507-
" VMOV D3, R2,R2 \n"
508-
" VMOV D4, R2,R2 \n"
509-
" VMOV D5, R2,R2 \n"
510-
" VMOV D6, R2,R2 \n"
511-
" VMOV D7, R2,R2 \n"
512-
" VMOV D8, R2,R2 \n"
513-
" VMOV D9, R2,R2 \n"
514-
" VMOV D10,R2,R2 \n"
515-
" VMOV D11,R2,R2 \n"
516-
" VMOV D12,R2,R2 \n"
517-
" VMOV D13,R2,R2 \n"
518-
" VMOV D14,R2,R2 \n"
519-
" VMOV D15,R2,R2 \n"
520-
521-
#ifdef __ARM_ADVANCED_SIMD__
522-
//Initialise D32 registers to 0
523-
" VMOV D16,R2,R2 \n"
524-
" VMOV D17,R2,R2 \n"
525-
" VMOV D18,R2,R2 \n"
526-
" VMOV D19,R2,R2 \n"
527-
" VMOV D20,R2,R2 \n"
528-
" VMOV D21,R2,R2 \n"
529-
" VMOV D22,R2,R2 \n"
530-
" VMOV D23,R2,R2 \n"
531-
" VMOV D24,R2,R2 \n"
532-
" VMOV D25,R2,R2 \n"
533-
" VMOV D26,R2,R2 \n"
534-
" VMOV D27,R2,R2 \n"
535-
" VMOV D28,R2,R2 \n"
536-
" VMOV D29,R2,R2 \n"
537-
" VMOV D30,R2,R2 \n"
538-
" VMOV D31,R2,R2 \n"
539-
#endif
540-
541-
//Initialise FPSCR to a known state
542-
" VMRS R1,FPSCR \n"
543-
" MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
544-
" AND R1,R1,R2 \n"
545-
" VMSR FPSCR,R1 \n"
546-
: : : "cc", "r1", "r2"
547-
);
548-
}
549-
550-
551-
552481
#undef __IAR_FT
553482
#undef __ICCARM_V8
554483

0 commit comments

Comments
 (0)