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Add missing ERRBNK definitions (#253)
Added missing L1 cache (Instruction & Data) Error bank register definitions from DDI0489B 3.3.10-11 Signed-off-by: Anubhav Raina <anubhav.raina@arm.com>
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‎CMSIS/Core/Include/core_cm7.h‎

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/*
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* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
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* Copyright (c) 2009-2025 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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/*@} end of group CMSIS_DCB */
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/**
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\ingroup CMSIS_core_register
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\defgroup CMSIS_ERRBNK Error Banking Registers (IMPLEMENTATION DEFINED)
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\brief Type definitions for the Error Banking Registers (ERRBNK)
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@{
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*/
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/**
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\brief Structure type to access the Error Banking Registers (ERRBNK).
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*/
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typedef struct {
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__IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */
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__IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */
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__IOM uint32_t DEBR0; /*!< Offset: 0x008 (R/W) Data Cache Error Bank Register 0 */
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__IOM uint32_t DEBR1; /*!< Offset: 0x00C (R/W) Data Cache Error Bank Register 1 */
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} ErrBnk_Type;
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/** \brief IEBR0 bit position and mask definitions */
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#define ERRBNK_IEBR0_USER_Pos 30U /*!< IEBR0: USER Position */
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#define ERRBNK_IEBR0_USER_Msk (0x3UL << ERRBNK_IEBR0_USER_Pos) /*!< IEBR0: USER Mask */
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#define ERRBNK_IEBR0_TYPE_Pos 17U /*!< IEBR0: TYPE Position */
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#define ERRBNK_IEBR0_TYPE_Msk (0x1UL << ERRBNK_IEBR0_TYPE_Pos) /*!< IEBR0: TYPE Mask */
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#define ERRBNK_IEBR0_RAMBank_Pos 16U /*!< IEBR0: RAMBANK Position */
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#define ERRBNK_IEBR0_RAMBank_Msk (0x1UL << ERRBNK_IEBR0_RAMBank_Pos) /*!< IEBR0: RAMBANK Mask */
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#define ERRBNK_IEBR0_WAY_Pos 14U /*!< IEBR0: WAY Position */
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#define ERRBNK_IEBR0_WAY_Msk (0x1UL << ERRBNK_IEBR0_WAY_Pos) /*!< IEBR0: WAY Mask */
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#define ERRBNK_IEBR0_INDEX_Pos 4U /*!< IEBR0: INDEX Position */
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#define ERRBNK_IEBR0_INDEX_Msk (0x3FFUL << ERRBNK_IEBR0_INDEX_Pos) /*!< IEBR0: INDEX Mask */
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#define ERRBNK_IEBR0_LDO_Pos 2U /*!< IEBR0: LDO Position */
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#define ERRBNK_IEBR0_LDO_Msk (0x3UL << ERRBNK_IEBR0_LDO_Pos) /*!< IEBR0: LDO Mask */
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#define ERRBNK_IEBR0_LOCK_Pos 1U /*!< IEBR0: LOCK Position */
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#define ERRBNK_IEBR0_LOCK_Msk (0x1UL << ERRBNK_IEBR0_LOCK_Pos) /*!< IEBR0: LOCK Mask */
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#define ERRBNK_IEBR0_VALID_Pos 0U /*!< IEBR0: VALID Position */
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#define ERRBNK_IEBR0_VALID_Msk (0x1UL << ERRBNK_IEBR0_VALID_Pos) /*!< IEBR0: VALID Mask */
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/** \brief IEBR1 bit position and mask definitions */
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#define ERRBNK_IEBR1_USER_Pos 30U /*!< IEBR1: USER Position */
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#define ERRBNK_IEBR1_USER_Msk (0x3UL << ERRBNK_IEBR1_USER_Pos) /*!< IEBR1: USER Mask */
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#define ERRBNK_IEBR1_TYPE_Pos 17U /*!< IEBR1: TYPE Position */
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#define ERRBNK_IEBR1_TYPE_Msk (0x1UL << ERRBNK_IEBR1_TYPE_Pos) /*!< IEBR1: TYPE Mask */
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#define ERRBNK_IEBR1_RAMBank_Pos 16U /*!< IEBR1: RAMBANK Position */
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#define ERRBNK_IEBR1_RAMBank_Msk (0x1UL << ERRBNK_IEBR1_RAMBank_Pos) /*!< IEBR1: RAMBANK Mask */
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#define ERRBNK_IEBR1_WAY_Pos 14U /*!< IEBR1: WAY Position */
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#define ERRBNK_IEBR1_WAY_Msk (0x1UL << ERRBNK_IEBR1_WAY_Pos) /*!< IEBR1: WAY Mask */
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#define ERRBNK_IEBR1_INDEX_Pos 4U /*!< IEBR1: INDEX Position */
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#define ERRBNK_IEBR1_INDEX_Msk (0x3FFUL << ERRBNK_IEBR1_INDEX_Pos) /*!< IEBR1: INDEX Mask */
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#define ERRBNK_IEBR1_LDO_Pos 2U /*!< IEBR1: LDO Position */
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#define ERRBNK_IEBR1_LDO_Msk (0x3UL << ERRBNK_IEBR1_LDO_Pos) /*!< IEBR1: LDO Mask */
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#define ERRBNK_IEBR1_LOCK_Pos 1U /*!< IEBR1: LOCK Position */
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#define ERRBNK_IEBR1_LOCK_Msk (0x1UL << ERRBNK_IEBR1_LOCK_Pos) /*!< IEBR1: LOCK Mask */
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#define ERRBNK_IEBR1_VALID_Pos 0U /*!< IEBR1: VALID Position */
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#define ERRBNK_IEBR1_VALID_Msk (0x1UL << ERRBNK_IEBR1_VALID_Pos) /*!< IEBR1: VALID Mask */
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/** \brief DEBR0 bit position and mask definitions */
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#define ERRBNK_DEBR0_USER_Pos 30U /*!< DEBR0: USER Position */
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#define ERRBNK_DEBR0_USER_Msk (0x3UL << ERRBNK_DEBR0_USER_Pos) /*!< DEBR0: USER Mask */
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#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< DEBR0: TYPE Position */
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#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< DEBR0: TYPE Mask */
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#define ERRBNK_DEBR0_RAMBank_Pos 16U /*!< DEBR0: RAMBANK Position */
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#define ERRBNK_DEBR0_RAMBank_Msk (0x1UL << ERRBNK_DEBR0_RAMBank_Pos) /*!< DEBR0: RAMBANK Mask */
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#define ERRBNK_DEBR0_WAY_Pos 14U /*!< DEBR0: WAY Position */
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#define ERRBNK_DEBR0_WAY_Msk (0x1UL << ERRBNK_DEBR0_WAY_Pos) /*!< DEBR0: WAY Mask */
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#define ERRBNK_DEBR0_INDEX_Pos 4U /*!< DEBR0: INDEX Position */
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#define ERRBNK_DEBR0_INDEX_Msk (0x3FFUL << ERRBNK_DEBR0_INDEX_Pos) /*!< DEBR0: INDEX Mask */
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#define ERRBNK_DEBR0_LDO_Pos 2U /*!< DEBR0: LDO Position */
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#define ERRBNK_DEBR0_LDO_Msk (0x3UL << ERRBNK_DEBR0_LDO_Pos) /*!< DEBR0: LDO Mask */
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#define ERRBNK_DEBR0_LOCK_Pos 1U /*!< DEBR0: LOCK Position */
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#define ERRBNK_DEBR0_LOCK_Msk (0x1UL << ERRBNK_DEBR0_LOCK_Pos) /*!< DEBR0: LOCK Mask */
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#define ERRBNK_DEBR0_VALID_Pos 0U /*!< DEBR0: VALID Position */
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#define ERRBNK_DEBR0_VALID_Msk (0x1UL << ERRBNK_DEBR0_VALID_Pos) /*!< DEBR0: VALID Mask */
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/** \brief DEBR1 bit position and mask definitions */
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#define ERRBNK_DEBR1_USER_Pos 30U /*!< DEBR1: USER Position */
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#define ERRBNK_DEBR1_USER_Msk (0x3UL << ERRBNK_DEBR1_USER_Pos) /*!< DEBR1: USER Mask */
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#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< DEBR1: TYPE Position */
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#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< DEBR1: TYPE Mask */
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#define ERRBNK_DEBR1_RAMBank_Pos 16U /*!< DEBR1: RAMBANK Position */
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#define ERRBNK_DEBR1_RAMBank_Msk (0x1UL << ERRBNK_DEBR1_RAMBank_Pos) /*!< DEBR1: RAMBANK Mask */
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#define ERRBNK_DEBR1_WAY_Pos 14U /*!< DEBR1: WAY Position */
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#define ERRBNK_DEBR1_WAY_Msk (0x1UL << ERRBNK_DEBR1_WAY_Pos) /*!< DEBR1: WAY Mask */
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#define ERRBNK_DEBR1_INDEX_Pos 4U /*!< DEBR1: INDEX Position */
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#define ERRBNK_DEBR1_INDEX_Msk (0x3FFUL << ERRBNK_DEBR1_INDEX_Pos) /*!< DEBR1: INDEX Mask */
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#define ERRBNK_DEBR1_LDO_Pos 2U /*!< DEBR1: LDO Position */
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#define ERRBNK_DEBR1_LDO_Msk (0x3UL << ERRBNK_DEBR1_LDO_Pos) /*!< DEBR1: LDO Mask */
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#define ERRBNK_DEBR1_LOCK_Pos 1U /*!< DEBR1: LOCK Position */
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#define ERRBNK_DEBR1_LOCK_Msk (0x1UL << ERRBNK_DEBR1_LOCK_Pos) /*!< DEBR1: LOCK Mask */
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#define ERRBNK_DEBR1_VALID_Pos 0U /*!< DEBR1: VALID Position */
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#define ERRBNK_DEBR1_VALID_Msk (0x1UL << ERRBNK_DEBR1_VALID_Pos) /*!< DEBR1: VALID Mask */
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/*@} end of group CMSIS_ERRBNK */
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/**
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\ingroup CMSIS_core_register
@@ -1777,6 +1895,7 @@ typedef struct
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#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
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#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
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#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
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#define ERRBNK_BASE (SCS_BASE + 0x0FB0UL) /*!< Error Banking Base Address */
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#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
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#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
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#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
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#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
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#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
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#define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
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#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */

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