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JonatanAntoniJonatanAntoni
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Fix CodeQL issues
1 parent b7a15a7 commit fc28c8d

12 files changed

Lines changed: 51 additions & 61 deletions

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‎CMSIS/Core/Include/a-profile/cmsis_cp15.h‎

Lines changed: 4 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -22,15 +22,15 @@
2222
* limitations under the License.
2323
*/
2424

25+
#ifndef __CMSIS_CP15_H
26+
#define __CMSIS_CP15_H
27+
2528
#if defined ( __ICCARM__ )
2629
#pragma system_include /* treat file as system include file for MISRA check */
2730
#elif defined (__clang__)
2831
#pragma clang system_header /* treat file as system include file */
2932
#endif
3033

31-
#ifndef __CMSIS_CP15_H
32-
#define __CMSIS_CP15_H
33-
3434
/** \brief Get ACTLR
3535
\return Auxiliary Control register value
3636
*/
@@ -253,8 +253,7 @@ __STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
253253
__set_CP(15, 0, mvbar, 12, 0, 1);
254254
}
255255

256-
#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
257-
defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
256+
#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
258257
defined(DOXYGEN)
259258

260259
/** \brief Set CNTFRQ
@@ -432,7 +431,6 @@ __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
432431
*/
433432
__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
434433
{
435-
// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
436434
__set_CP(15, 2, value, 0, 0, 0);
437435
}
438436

@@ -442,27 +440,16 @@ __STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
442440
__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
443441
{
444442
uint32_t result;
445-
// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
446443
__get_CP(15, 2, result, 0, 0, 0);
447444
return result;
448445
}
449446

450-
/** \brief Set CCSIDR
451-
\deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
452-
*/
453-
CMSIS_DEPRECATED
454-
__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
455-
{
456-
__set_CSSELR(value);
457-
}
458-
459447
/** \brief Get CCSIDR
460448
\return CCSIDR Register value
461449
*/
462450
__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
463451
{
464452
uint32_t result;
465-
// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
466453
__get_CP(15, 1, result, 0, 0, 0);
467454
return result;
468455
}
@@ -473,7 +460,6 @@ __STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
473460
__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
474461
{
475462
uint32_t result;
476-
// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
477463
__get_CP(15, 1, result, 0, 0, 1);
478464
return result;
479465
}
@@ -482,23 +468,20 @@ __STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
482468
*/
483469
__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
484470
{
485-
// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
486471
__set_CP(15, 0, value, 7, 6, 2);
487472
}
488473

489474
/** \brief Set DCCSW
490475
*/
491476
__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
492477
{
493-
// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
494478
__set_CP(15, 0, value, 7, 10, 2);
495479
}
496480

497481
/** \brief Set DCCISW
498482
*/
499483
__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
500484
{
501-
// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
502485
__set_CP(15, 0, value, 7, 14, 2);
503486
}
504487

‎CMSIS/Core/Include/a-profile/irq_ctrl.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,15 +22,15 @@
2222
* limitations under the License.
2323
*/
2424

25+
#ifndef IRQ_CTRL_H_
26+
#define IRQ_CTRL_H_
27+
2528
#if defined ( __ICCARM__ )
2629
#pragma system_include /* treat file as system include file for MISRA check */
2730
#elif defined (__clang__)
2831
#pragma clang system_header /* treat file as system include file */
2932
#endif
3033

31-
#ifndef IRQ_CTRL_H_
32-
#define IRQ_CTRL_H_
33-
3434
#include <stdint.h>
3535

3636
#ifndef IRQHANDLER_T

‎CMSIS/Core/Include/core_ca.h‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -22,15 +22,15 @@
2222
* limitations under the License.
2323
*/
2424

25+
#ifndef __CORE_CA_H_GENERIC
26+
#define __CORE_CA_H_GENERIC
27+
2528
#if defined ( __ICCARM__ )
2629
#pragma system_include /* treat file as system include file for MISRA check */
2730
#elif defined (__clang__)
2831
#pragma clang system_header /* treat file as system include file */
2932
#endif
3033

31-
#ifndef __CORE_CA_H_GENERIC
32-
#define __CORE_CA_H_GENERIC
33-
3434
#ifdef __cplusplus
3535
extern "C" {
3636
#endif
@@ -131,6 +131,12 @@
131131
#ifndef __CORE_CA_H_DEPENDANT
132132
#define __CORE_CA_H_DEPENDANT
133133

134+
#if defined ( __ICCARM__ )
135+
#pragma system_include /* treat file as system include file for MISRA check */
136+
#elif defined (__clang__)
137+
#pragma clang system_header /* treat file as system include file */
138+
#endif
139+
134140
#ifdef __cplusplus
135141
extern "C" {
136142
#endif
@@ -675,7 +681,8 @@ typedef union
675681
/**
676682
\brief Union type to access the L2C_310 Cache Controller.
677683
*/
678-
#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
684+
#if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \
685+
defined(DOXYGEN)
679686
typedef struct
680687
{
681688
__IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */
@@ -738,7 +745,8 @@ typedef struct
738745
#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
739746
#endif
740747

741-
#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
748+
#if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \
749+
defined(DOXYGEN)
742750

743751
/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
744752
*/
@@ -1078,7 +1086,8 @@ typedef struct
10781086
#define GICInterface_DIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk)
10791087
#endif /* (__GIC_PRESENT == 1U) || defined(DOXYGEN) */
10801088

1081-
#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
1089+
#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
1090+
defined(DOXYGEN)
10821091
#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
10831092
/** \brief Structure type to access the Private Timer
10841093
*/
@@ -1280,7 +1289,7 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma
12801289
uint32_t num_ways;
12811290
uint32_t shift_way;
12821291
uint32_t log2_linesize;
1283-
int32_t log2_num_ways;
1292+
uint8_t log2_num_ways;
12841293

12851294
Dummy = level << 1U;
12861295
/* set csselr, select ccsidr register */
@@ -1291,10 +1300,10 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma
12911300
num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
12921301
log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
12931302
log2_num_ways = __log2_up(num_ways);
1294-
if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
1303+
if (log2_num_ways > 32U) {
12951304
return; // FATAL ERROR
12961305
}
1297-
shift_way = 32U - (uint32_t)log2_num_ways;
1306+
shift_way = 32U - log2_num_ways;
12981307
for(int32_t way = num_ways-1; way >= 0; way--)
12991308
{
13001309
for(int32_t set = num_sets-1; set >= 0; set--)
@@ -1358,7 +1367,8 @@ __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
13581367
}
13591368

13601369
/* ########################## L2 Cache functions ################################# */
1361-
#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
1370+
#if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \
1371+
defined(DOXYGEN)
13621372
/** \brief Cache Sync operation by writing CACHE_SYNC register.
13631373
*/
13641374
__STATIC_INLINE void L2C_Sync(void)
@@ -1468,7 +1478,8 @@ __STATIC_INLINE void L2C_CleanInvPa (void *pa)
14681478
#endif
14691479

14701480
/* ########################## GIC functions ###################################### */
1471-
#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
1481+
#if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \
1482+
defined(DOXYGEN)
14721483

14731484
/** \brief Enable the interrupt distributor using the GIC's CTLR register.
14741485
*/
@@ -1854,7 +1865,8 @@ __STATIC_INLINE void GIC_Enable(void)
18541865
#endif
18551866

18561867
/* ########################## Generic Timer functions ############################ */
1857-
#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
1868+
#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
1869+
defined(DOXYGEN)
18581870

18591871
/* PL1 Physical Timer */
18601872
#if (__CORTEX_A == 7U) || defined(DOXYGEN)

‎CMSIS/Core/Include/core_cm0.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -581,7 +581,7 @@ typedef struct
581581
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
582582
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
583583
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
584-
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
584+
/* NVIC_GetActive not available for Cortex-M0 */
585585
#define NVIC_SetPriority __NVIC_SetPriority
586586
#define NVIC_GetPriority __NVIC_GetPriority
587587
#define NVIC_SystemReset __NVIC_SystemReset

‎CMSIS/Core/Include/core_cm0plus.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -699,7 +699,7 @@ typedef struct
699699
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
700700
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
701701
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
702-
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
702+
/* NVIC_GetActive not available for Cortex-M0+ */
703703
#define NVIC_SetPriority __NVIC_SetPriority
704704
#define NVIC_GetPriority __NVIC_GetPriority
705705
#define NVIC_SystemReset __NVIC_SystemReset

‎CMSIS/Core/Include/core_cm23.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1458,8 +1458,8 @@ typedef struct
14581458
#endif
14591459
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
14601460
#else
1461-
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
1462-
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
1461+
/* NVIC_SetPriorityGrouping not available for Cortex-M23 */
1462+
/* NVIC_GetPriorityGrouping not available for Cortex-M23 */
14631463
#define NVIC_EnableIRQ __NVIC_EnableIRQ
14641464
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
14651465
#define NVIC_DisableIRQ __NVIC_DisableIRQ

‎CMSIS/Core/Include/m-profile/armv7m_cachel1.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,15 +22,15 @@
2222
* limitations under the License.
2323
*/
2424

25+
#ifndef ARM_ARMV7M_CACHEL1_H
26+
#define ARM_ARMV7M_CACHEL1_H
27+
2528
#if defined ( __ICCARM__ )
2629
#pragma system_include /* treat file as system include file for MISRA check */
2730
#elif defined (__clang__)
2831
#pragma clang system_header /* treat file as system include file */
2932
#endif
3033

31-
#ifndef ARM_ARMV7M_CACHEL1_H
32-
#define ARM_ARMV7M_CACHEL1_H
33-
3434
/**
3535
\ingroup CMSIS_Core_FunctionInterface
3636
\defgroup CMSIS_Core_CacheFunctions Cache Functions

‎CMSIS/Core/Include/m-profile/armv7m_mpu.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,15 +22,15 @@
2222
* limitations under the License.
2323
*/
2424

25+
#ifndef ARM_MPU_ARMV7_H
26+
#define ARM_MPU_ARMV7_H
27+
2528
#if defined ( __ICCARM__ )
2629
#pragma system_include /* treat file as system include file for MISRA check */
2730
#elif defined (__clang__)
2831
#pragma clang system_header /* treat file as system include file */
2932
#endif
3033

31-
#ifndef ARM_MPU_ARMV7_H
32-
#define ARM_MPU_ARMV7_H
33-
3434
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
3535
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
3636
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes

‎CMSIS/Core/Include/m-profile/armv81m_pac.h‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,16 +22,15 @@
2222
* limitations under the License.
2323
*/
2424

25+
#ifndef PAC_ARMV81_H
26+
#define PAC_ARMV81_H
27+
2528
#if defined ( __ICCARM__ )
2629
#pragma system_include /* treat file as system include file for MISRA check */
2730
#elif defined (__clang__)
2831
#pragma clang system_header /* treat file as system include file */
2932
#endif
3033

31-
#ifndef PAC_ARMV81_H
32-
#define PAC_ARMV81_H
33-
34-
3534
/* ################### PAC Key functions ########################### */
3635
/**
3736
\ingroup CMSIS_Core_FunctionInterface

‎CMSIS/Core/Include/m-profile/armv8m_mpu.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,15 +22,15 @@
2222
* limitations under the License.
2323
*/
2424

25+
#ifndef ARM_MPU_ARMV8_H
26+
#define ARM_MPU_ARMV8_H
27+
2528
#if defined ( __ICCARM__ )
2629
#pragma system_include /* treat file as system include file for MISRA check */
2730
#elif defined (__clang__)
2831
#pragma clang system_header /* treat file as system include file */
2932
#endif
3033

31-
#ifndef ARM_MPU_ARMV8_H
32-
#define ARM_MPU_ARMV8_H
33-
3434
/** \brief Attribute for device memory (outer only) */
3535
#define ARM_MPU_ATTR_DEVICE ( 0U )
3636

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