From f663ed01a30ad41ffa871c043368df000ec5c7c2 Mon Sep 17 00:00:00 2001 From: Murat Hepeyiler Date: Thu, 23 Oct 2025 10:15:46 +0200 Subject: [PATCH] Issue #264: cmsis_iccarm.h prototype fix Signed-off-by: Murat Hepeyiler --- CMSIS/Core/Include/cmsis_iccarm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/CMSIS/Core/Include/cmsis_iccarm.h b/CMSIS/Core/Include/cmsis_iccarm.h index 722126e34..9c45ccacf 100644 --- a/CMSIS/Core/Include/cmsis_iccarm.h +++ b/CMSIS/Core/Include/cmsis_iccarm.h @@ -243,7 +243,7 @@ __IAR_FT int16_t __REVSH(int16_t val) * Fixed in EWARM 9.50.i2 */ -__IAR_FT void __CLREX() { +__IAR_FT void __CLREX(void) { __ASM volatile("CLREX" ::: "memory"); } @@ -464,12 +464,12 @@ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) // This is not really fault_irq on Cortex-not-M. However // there seems to be code that assumes this. - __IAR_FT void __disable_fault_irq() + __IAR_FT void __disable_fault_irq(void) { __ASM volatile ("CPSID F" ::: "memory"); } - __IAR_FT void __enable_fault_irq() + __IAR_FT void __enable_fault_irq(void) { __ASM volatile ("CPSIE F" ::: "memory"); }