Add TI Arm Clang Compiler Support to CMSIS Core Validation

.github/workflows/corevalidation.yml

@@ -21,12 +21,16 @@ jobs:
     strategy:
       fail-fast: true
       matrix:
-        compiler: [AC6, GCC, Clang]
+        compiler: [AC6, GCC, Clang, Clang_TI]
 
     runs-on: ubuntu-22.04
 
     env:
       ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }}
+      CLANG_TI_VERSION: "5.1.0.LTS"
+      CLANG_TI_TC_SUFFIX: "5_1_0"
+      CLANG_TI_INSTALL_PATH: "/home/runner/"
+      CLANG_TI_SHA256: "c758668b78c080be5ec75393cdd09d077742fd1183aa0c181318a0119d58c4d0"
 
     steps:
       - run: |
@@ -81,7 +85,31 @@ jobs:
           queries: security-and-quality
 
       - uses: ammaraskar/gcc-problem-matcher@master
-        if: matrix.compiler == 'Clang' || matrix.compiler == 'GCC'
+        if: matrix.compiler == 'Clang' || matrix.compiler == 'Clang_TI' || matrix.compiler == 'GCC'
+
+      - name: Set TI ARM CLANG Environment Variables and Path
+        run: |
+          echo "CLANG_TI_PATH=${{ env.CLANG_TI_INSTALL_PATH }}ti-cgt-armllvm_${{ env.CLANG_TI_VERSION }}" >> $GITHUB_ENV
+          echo "CLANG_TI_TOOLCHAIN_${{ env.CLANG_TI_TC_SUFFIX }}=${{ env.CLANG_TI_INSTALL_PATH }}ti-cgt-armllvm_${{ env.CLANG_TI_VERSION }}/bin" >> $GITHUB_ENV
+
+      - name: Cache TI ARM CLANG
+        id: cache-ti-arm-clang
+        uses: actions/cache@v5
+        with:
+          path: ${{ env.CLANG_TI_PATH }}
+          key: ${{ runner.os }}-ti-arm-clang-${{ env.CLANG_TI_VERSION }}
+
+      - name: Download and Verify TI ARM CLANG Installer
+        working-directory: /home/runner
+        if: steps.cache-ti-arm-clang.outputs.cache-hit != 'true'
+        run: |
+          FILE="ti_cgt_armllvm_${{ env.CLANG_TI_VERSION }}_linux-x64_installer.bin"
+          URL="https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-ayxs93eZNN/${{ env.CLANG_TI_VERSION }}/${FILE}"
+
+          curl -L "$URL" -o "$FILE"
+          echo "${{ env.CLANG_TI_SHA256 }}  $FILE" | sha256sum --check
+          chmod +x "$FILE"
+          ./"$FILE" --mode unattended --prefix "${{ env.CLANG_TI_INSTALL_PATH }}"
 
       - name: Build
         working-directory: ./CMSIS/CoreValidation/Project
@@ -98,7 +126,7 @@ jobs:
 
       - name: Execute
         working-directory: ./CMSIS/CoreValidation/Project
-        run: |     
+        run: |
           echo "Run test projects ..."
           ./build.py --verbose -c ${{ matrix.compiler }} -d "CM*" run || echo "::warning::==== Some configurations failed to run! ==="
 

CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml

@@ -11,6 +11,7 @@ layer:
   add-path:
     - ../../../Include
     - ../../../Source/Config
+    - ../../../Source/Clang_TI_Semihost
 
   misc:
     - for-compiler: AC6
@@ -69,3 +70,8 @@ layer:
       files:
         - file: ../../../Source/CV_Framework.c
         - file: ../../../Source/CV_Report.c
+
+    - group: TI Arm Clang Compiler Semihost Support
+      for-compiler: CLANG_TI
+      files:
+        - file: ../../../Source/Clang_TI_Semihost/clang_ti_semihost.c

CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/clang_ti_linker_script.cmd

@@ -0,0 +1,76 @@
+--stack_size=__STACK_SIZE
+--heap_size=__HEAP_SIZE
+--symbol_map=_start=_c_int00
+--entry_point=Reset_Handler
+--retain="*(.vectors)"
+--retain="*(.intvecs)"
+
+/* Macros for Stack/Seal */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define __STACKSEAL_SIZE 8
+#else
+  #define __STACKSEAL_SIZE 0
+#endif
+
+MEMORY
+{
+    ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+    RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+}
+
+SECTIONS
+{
+    /* 1. Vectors forced to the base of ROM */
+    .intvecs : load = __ROM0_BASE
+    {
+        *(.vectors)
+        *(.intvecs)
+    }
+
+    /* 2. Code and Read-Only Data */
+    .text       : {} > ROM0
+
+    /* 3. CMSE Veneers */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    Veneer$$CMSE : {} > ROM0
+#endif
+
+    .rodata     : {} > ROM0
+    .TI.crctab  : {} > ROM0
+
+    /* 4. Runtime Initialization Tables */
+    .binit      : {} > ROM0
+    .cinit      : {} > ROM0
+    .pinit      : {} > ROM0
+    .init_array : {} > ROM0
+    .fini_array : {} > ROM0
+    .ovly       : {} > ROM0
+
+    /* 5. Initialized Data */
+    .data       : load = ROM0, run = RAM0, table(BINIT)
+
+    /* 6. Uninitialized Data */
+    .bss        : type = NOINIT {} > RAM0
+    .sysmem     : type = NOINIT {} > RAM0
+
+    /* 7. Stack & Security Seal */
+    /* (HIGH) ensures these are placed at the end of RAM0 */
+    GROUP : > RAM0 (HIGH)
+    {
+        .stack : type = NOINIT, palign = 8
+        {
+            __stack_limit = .;
+            . += __STACK_SIZE;
+            __INITIAL_SP = .;       /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */
+            __stack      = . - 1;   /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1       */
+        }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+        .stackseal : type = NOINIT, palign = 8
+        {
+            __stack_seal = .;
+            . += __STACKSEAL_SIZE;
+        }
+#endif
+    }
+}

CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml

@@ -22,6 +22,9 @@ layer:
     - for-compiler: CLANG
       script: RTE/Device/$Dname$/clang_linker_script.ld
       regions: RTE/Device/$Dname$/regions_$Dname$.h
+    - for-compiler: CLANG_TI
+      script: RTE/Device/$Dname$/clang_ti_linker_script.cmd
+      regions: RTE/Device/$Dname$/regions_$Dname$.h
     - for-compiler: IAR
       script: RTE/Device/$Dname$/iar_linker_script.icf
       regions: RTE/Device/$Dname$/regions_$Dname$.h

CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/clang_ti_linker_script.cmd

@@ -0,0 +1,76 @@
+--stack_size=__STACK_SIZE
+--heap_size=__HEAP_SIZE
+--symbol_map=_start=_c_int00
+--entry_point=Reset_Handler
+--retain="*(.vectors)"
+--retain="*(.intvecs)"
+
+/* Macros for Stack/Seal */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define __STACKSEAL_SIZE 8
+#else
+  #define __STACKSEAL_SIZE 0
+#endif
+
+MEMORY
+{
+    ROM0 (RX) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+    RAM0 (RW) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+}
+
+SECTIONS
+{
+    /* 1. Vectors forced to the base of ROM */
+    .intvecs : load = __ROM0_BASE
+    {
+        *(.vectors)
+        *(.intvecs)
+    }
+
+    /* 2. Code and Read-Only Data */
+    .text       : {} > ROM0
+
+    /* 3. CMSE Veneers */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    Veneer$$CMSE : {} > ROM0
+#endif
+
+    .rodata     : {} > ROM0
+    .TI.crctab  : {} > ROM0
+
+    /* 4. Runtime Initialization Tables */
+    .binit      : {} > ROM0
+    .cinit      : {} > ROM0
+    .pinit      : {} > ROM0
+    .init_array : {} > ROM0
+    .fini_array : {} > ROM0
+    .ovly       : {} > ROM0
+
+    /* 5. Initialized Data */
+    .data       : load = ROM0, run = RAM0, table(BINIT)
+
+    /* 6. Uninitialized Data */
+    .bss        : type = NOINIT {} > RAM0
+    .sysmem     : type = NOINIT {} > RAM0
+
+    /* 7. Stack & Security Seal */
+    /* (HIGH) ensures these are placed at the end of RAM0 */
+    GROUP : > RAM0 (HIGH)
+    {
+        .stack : type = NOINIT, palign = 8
+        {
+            __stack_limit = .;
+            . += __STACK_SIZE;
+            __INITIAL_SP = .;       /* CMSIS startup: initial SP loaded from vector table (8-byte aligned) */
+            __stack      = . - 1;   /* TI CRT _c_int00 compatibility: CRT computes SP = __stack + 1       */
+        }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+        .stackseal : type = NOINIT, palign = 8
+        {
+            __stack_seal = .;
+            . += __STACKSEAL_SIZE;
+        }
+#endif
+    }
+}

CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml

@@ -22,6 +22,9 @@ layer:
     - for-compiler: CLANG
       script: RTE/Device/$Dname$/clang_linker_script.ld
       regions: RTE/Device/$Dname$/regions_$Dname$.h
+    - for-compiler: CLANG_TI
+      script: RTE/Device/$Dname$/clang_ti_linker_script.cmd
+      regions: RTE/Device/$Dname$/regions_$Dname$.h
     - for-compiler: IAR
       script: RTE/Device/$Dname$/iar_linker_script.icf
       regions: RTE/Device/$Dname$/regions_$Dname$.h