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Short-circuit dcache disable#293

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JonatanAntoni merged 1 commit intoARM-software:mainfrom
satur9nine:disable-dcache-fix
Apr 20, 2026
Merged

Short-circuit dcache disable#293
JonatanAntoni merged 1 commit intoARM-software:mainfrom
satur9nine:disable-dcache-fix

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@satur9nine satur9nine commented Apr 16, 2026

Do not attempt to clean and invalidate the DCache if SCB_DisableDCache is invoked when it was not enabled in the first place. This prevents landing junk into RAM after a POR.

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Pull request overview

This PR prevents SCB_DisableDCache() from performing a clean+invalidate sequence when the D-cache is already disabled, avoiding potential write-back of undefined cache contents after a power-on reset (POR).

Changes:

  • Added an early-return guard in SCB_DisableDCache() when SCB->CCR.DC is not set.

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Comment thread CMSIS/Core/Include/m-profile/armv7m_cachel1.h
Comment thread CMSIS/Core/Include/m-profile/armv7m_cachel1.h Outdated
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github-actions Bot commented Apr 17, 2026

Test Results

   292 files   -    352     292 suites   - 352   0s ⏱️ - 14m 47s
    56 tests +     7      54 ✅ +   10      2 💤  -     3  0 ❌ ±0 
15 768 runs   - 15 788  13 264 ✅  - 6 892  2 504 💤  - 8 896  0 ❌ ±0 

Results for commit b1b2bb5. ± Comparison against base commit f622607.

This pull request removes 49 and adds 56 tests. Note that renamed tests count towards both.
CMSIS-Core.src ‑ apsr.c
CMSIS-Core.src ‑ basepri.c
CMSIS-Core.src ‑ bkpt.c
CMSIS-Core.src ‑ clrex.c
CMSIS-Core.src ‑ clz.c
CMSIS-Core.src ‑ control.c
CMSIS-Core.src ‑ cp15.c
CMSIS-Core.src ‑ cpsr.c
CMSIS-Core.src ‑ dmb.c
CMSIS-Core.src ‑ dsb.c
…
TC_CML1Cache_CleanDCacheByAddrWhileDisabled
TC_CML1Cache_EnDisableDCache
TC_CML1Cache_EnDisableICache
TC_CoreFunc_APSR
TC_CoreFunc_BASEPRI
TC_CoreFunc_Control
TC_CoreFunc_EnDisIRQ
TC_CoreFunc_EncDecIRQPrio
TC_CoreFunc_FAULTMASK
TC_CoreFunc_FPSCR
…
This pull request removes 5 skipped tests and adds 2 skipped tests. Note that renamed tests count towards both.
CMSIS-Core.src ‑ lda.c
CMSIS-Core.src ‑ ldaex.c
CMSIS-Core.src ‑ stl.c
CMSIS-Core.src ‑ stlex.c
CMSIS-Core.src ‑ systick.c
TC_CoreInstr_WFE
TC_CoreInstr_WFI

♻️ This comment has been updated with latest results.

Do not attempt to clean and invalidate the DCache if SCB_DisableDCache is
invoked when it was not enabled in the first place. This prevents landing
junk into RAM after a POR.
@JonatanAntoni JonatanAntoni merged commit 2d1af12 into ARM-software:main Apr 20, 2026
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3 participants