fix: Don't skip Im2Col if convolution has paddings

Resolves: ARMCL-1254
Issue: #1253
Change-Id: I8c88dde1fd4df69f4a7eaf8ad4125462c09dda3f
Signed-off-by: Gunes Bayir <gunes.bayir@arm.com>

Author: gunes-arm

src/cpu/operators/CpuGemmConv2d.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2025 Arm Limited.
+ * Copyright (c) 2021-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -185,8 +185,10 @@ CpuGemmConv2d::SkipInfo CpuGemmConv2d::skip_im_col_info(const ITensorInfo
     unsigned int       conv_h        = 0;
     std::tie(conv_w, conv_h) = scaled_dimensions(src->dimension(idx_width), src->dimension(idx_height), kernel_width,
                                                  kernel_height, conv_info, dilation);
-    const bool skip_im2col   = (data_layout == DataLayout::NHWC && kernel_width == 1 && kernel_height == 1 &&
-                              conv_info.stride().first == 1 && conv_info.stride().second == 1);
+
+    const bool skip_im2col = (data_layout == DataLayout::NHWC && kernel_width == 1 && kernel_height == 1 &&
+                              conv_info.stride().first == 1 && conv_info.stride().second == 1) &&
+                             !conv_info.has_padding();
 
     if (skip_im2col)
     {

src/gpu/cl/operators/ClGemmConv2d.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, 2023 Arm Limited.
+ * Copyright (c) 2017-2021, 2023, 2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -214,8 +214,9 @@ void ClGemmConv2d::configure(const CLCompileContext &compile_context,
     _is_prepared  = weights_info.retain_internal_weights();
     _is_quantized = is_data_type_quantized_asymmetric(src->data_type());
     _skip_im2col  = (data_layout == DataLayout::NHWC && kernel_width == 1 && kernel_height == 1 &&
-                    conv2d_info.conv_info.stride().first == 1 && conv2d_info.conv_info.stride().second == 1);
-    _skip_col2im  = data_layout == DataLayout::NHWC;
+                    conv2d_info.conv_info.stride().first == 1 && conv2d_info.conv_info.stride().second == 1) &&
+                   !conv2d_info.conv_info.has_padding();
+    _skip_col2im = data_layout == DataLayout::NHWC;
 
     // Only for quantize there are few cases where we cannot fuse the activation function in GEMM
     _fuse_activation = true;
@@ -419,10 +420,12 @@ Status ClGemmConv2d::validate(const ITensorInfo *src,
     const ITensorInfo *gemm_output_to_use = dst;
     const ITensorInfo *weights_to_use     = weights;
     const bool         is_quantized       = is_data_type_quantized_asymmetric(data_type);
-    const bool         skip_im2col     = (data_layout == DataLayout::NHWC && kernel_width == 1 && kernel_height == 1 &&
-                              conv2d_info.conv_info.stride().first == 1 && conv2d_info.conv_info.stride().second == 1);
-    const bool         skip_col2im     = data_layout == DataLayout::NHWC;
-    bool               fuse_activation = true;
+    const bool         skip_im2col =
+        (data_layout == DataLayout::NHWC && kernel_width == 1 && kernel_height == 1 &&
+         conv2d_info.conv_info.stride().first == 1 && conv2d_info.conv_info.stride().second == 1) &&
+        !conv2d_info.conv_info.has_padding();
+    const bool skip_col2im     = data_layout == DataLayout::NHWC;
+    bool       fuse_activation = true;
 
     ARM_COMPUTE_RETURN_ERROR_ON((weights->dimension(idx_channel) * conv2d_info.num_groups) !=
                                 src->dimension(idx_channel));

tests/datasets/SmallConvolutionLayerDataset.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, 2025 Arm Limited.
+ * Copyright (c) 2017-2021, 2025-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -181,6 +181,8 @@ class SmallConvolutionLayerDataset final : public ConvolutionLayerDataset
         // 1x1 Kernel with Stride (1, 1) and NHWC data layout in order to test skipping Im2Col
         add_config(TensorShape(1U, 5U, 2U), TensorShape(1U, 1U, 2U, 3U), TensorShape(3U), TensorShape(1U, 5U, 3U),
                    PadStrideInfo(1, 1, 0, 0));
+        add_config(TensorShape(1U, 5U, 2U), TensorShape(1U, 1U, 2U, 3U), TensorShape(3U), TensorShape(3U, 7U, 3U),
+                   PadStrideInfo(1, 1, 1, 1));
 
         // Batch size 1
         add_config(TensorShape(23U, 27U, 5U), TensorShape(3U, 3U, 5U, 2U), TensorShape(2U), TensorShape(11U, 25U, 2U),