feat: Add fine-grained SME feature flags.

DavidMansell · gunes-arm · commit 902f9a745429 · 2026-01-09T10:08:32.000Z
The ARM architecture defines distinct features for each outer product
data type.  Add these features, and detection code for bare metal (via
sysregs), Linux (via HWCAP2) and macOS (via sysctl).  For Windows,
assume that anything supporting SME also supports these features.

Signed-off-by: David Mansell &lt;David.Mansell@arm.com&gt;
Change-Id: Ia236714d51bb935fa366553dc9ac193d50c8d18a
diff --git a/arm_compute/core/CPP/CPPTypes.h b/arm_compute/core/CPP/CPPTypes.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, 2024-2025 Arm Limited.
+ * Copyright (c) 2017-2022, 2024-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -148,6 +148,26 @@ class CPUInfo final
      * @return true if the cpu supports sme2, false otherwise
      */
     bool has_sme2() const;
+    /** Checks if the cpu model supports sme_i8i32.
+     *
+     * @return true if the cpu supports sme_i8i32, false otherwise
+     */
+    bool has_sme_i8i32() const;
+    /** Checks if the cpu model supports sme_f16f32.
+     *
+     * @return true if the cpu supports sme_f16f32, false otherwise
+     */
+    bool has_sme_f16f32() const;
+    /** Checks if the cpu model supports sme_f32f32.
+     *
+     * @return true if the cpu supports sme_f32f32, false otherwise
+     */
+    bool has_sme_f32f32() const;
+    /** Checks if the cpu model supports sme_b16f32.
+     *
+     * @return true if the cpu supports sme_b16f32, false otherwise
+     */
+    bool has_sme_b16f32() const;
     /** Gets the cpu model for a given cpuid.
      *
      * @param[in] cpuid the id of the cpu core to be retrieved,
diff --git a/src/common/cpuinfo/CpuInfo.cpp b/src/common/cpuinfo/CpuInfo.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2025 Arm Limited.
+ * Copyright (c) 2021-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -344,6 +344,17 @@ uint64_t get_sve_feature_reg()
                      : "x3");
     return svefr0;
 }
+
+uint64_t get_sme_feature_reg()
+{
+    uint64_t smefr0 = 0;
+    __asm __volatile(".inst 0xd53804a3 // mrs x3, ID_AA64SMFR0_EL1\n"
+                     "MOV  %0, X3"
+                     : "=r"(smefr0)
+                     :
+                     : "x3");
+    return smefr0;
+}
 #endif /* defined(BARE_METAL) && defined(__aarch64__) */
 } // namespace
 
@@ -405,7 +416,7 @@ CpuInfo CpuInfo::build()
         __aarch64__) /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && !defined(__QNX__) && (defined(__arm__) || defined(__aarch64__)) */
 
     // Assume single CPU in bare metal mode.  Just read the ID register and feature bits directly.
-    uint64_t isar0 = 0, isar1 = 0, pfr0 = 0, pfr1 = 0, svefr0 = 0, midr = 0;
+    uint64_t isar0 = 0, isar1 = 0, pfr0 = 0, pfr1 = 0, svefr0 = 0, smefr0 = 0, midr = 0;
     ARM_COMPUTE_GET_FEATURE_REG(isar0, ID_AA64ISAR0_EL1);
     ARM_COMPUTE_GET_FEATURE_REG(isar1, ID_AA64ISAR1_EL1);
     ARM_COMPUTE_GET_FEATURE_REG(pfr0, ID_AA64PFR0_EL1);
@@ -415,8 +426,12 @@ CpuInfo CpuInfo::build()
     {
         svefr0 = get_sve_feature_reg();
     }
+    if ((pfr1 >> 24) & 0xf)
+    {
+        smefr0 = get_sme_feature_reg();
+    }
 
-    CpuIsaInfo            isa = init_cpu_isa_from_regs(isar0, isar1, pfr0, pfr1, svefr0, midr);
+    CpuIsaInfo            isa = init_cpu_isa_from_regs(isar0, isar1, pfr0, pfr1, svefr0, smefr0, midr);
     std::vector<CpuModel> cpus_model(1, midr_to_model(midr));
     CpuInfo               info(isa, cpus_model);
     return info;
@@ -425,13 +440,17 @@ CpuInfo CpuInfo::build()
     int                   ncpus = get_hw_capability("hw.perflevel0.logicalcpu");
     CpuIsaInfo            isainfo;
     std::vector<CpuModel> cpus_model(ncpus);
-    isainfo.neon = get_hw_capability("hw.optional.neon");
-    isainfo.fp16 = get_hw_capability("hw.optional.neon_fp16");
-    isainfo.dot  = get_hw_capability("hw.optional.arm.FEAT_DotProd");
-    isainfo.bf16 = get_hw_capability("hw.optional.arm.FEAT_BF16");
-    isainfo.i8mm = get_hw_capability("hw.optional.arm.FEAT_I8MM");
-    isainfo.sme  = get_hw_capability("hw.optional.arm.FEAT_SME");
-    isainfo.sme2 = get_hw_capability("hw.optional.arm.FEAT_SME2");
+    isainfo.neon       = get_hw_capability("hw.optional.neon");
+    isainfo.fp16       = get_hw_capability("hw.optional.neon_fp16");
+    isainfo.dot        = get_hw_capability("hw.optional.arm.FEAT_DotProd");
+    isainfo.bf16       = get_hw_capability("hw.optional.arm.FEAT_BF16");
+    isainfo.i8mm       = get_hw_capability("hw.optional.arm.FEAT_I8MM");
+    isainfo.sme        = get_hw_capability("hw.optional.arm.FEAT_SME");
+    isainfo.sme_f32f32 = get_hw_capability("hw.optional.arm.SME_F32F32");
+    isainfo.sme_b16f32 = get_hw_capability("hw.optional.arm.SME_B16F32");
+    isainfo.sme_f16f32 = get_hw_capability("hw.optional.arm.SME_F16F32");
+    isainfo.sme_i8i32  = get_hw_capability("hw.optional.arm.SME_I8I32");
+    isainfo.sme2       = get_hw_capability("hw.optional.arm.FEAT_SME2");
     CpuInfo info(isainfo, cpus_model);
     return info;
 #elif defined(__aarch64__) && defined(_WIN64)    /* #elif defined(__aarch64__) && defined(__APPLE__) */
@@ -441,6 +460,13 @@ CpuInfo CpuInfo::build()
     isainfo.sve  = IsProcessorFeaturePresent(PF_ARM_SVE_INSTRUCTIONS_AVAILABLE);
     isainfo.sve2 = IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE);
     isainfo.sme  = IsProcessorFeaturePresent(PF_ARM_SME_INSTRUCTIONS_AVAILABLE);
+
+    // These features are implied by FEAT_SME
+    isainfo.sme_f32f32 = isainfo.sme;
+    isainfo.sme_b16f32 = isainfo.sme;
+    isainfo.sme_f16f32 = isainfo.sme;
+    isainfo.sme_i8i32  = isainfo.sme;
+
     isainfo.sme2 = IsProcessorFeaturePresent(PF_ARM_SME2_INSTRUCTIONS_AVAILABLE);
     isainfo.fhm  = false; // constant not found
 
diff --git a/src/common/cpuinfo/CpuInfo.h b/src/common/cpuinfo/CpuInfo.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, 2024-2025 Arm Limited.
+ * Copyright (c) 2021-2022, 2024-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -83,6 +83,22 @@ class CpuInfo
     {
         return _isa.sme2;
     }
+    bool has_sme_i8i32() const
+    {
+        return _isa.sme_i8i32;
+    }
+    bool has_sme_f16f32() const
+    {
+        return _isa.sme_f16f32;
+    }
+    bool has_sme_f32f32() const
+    {
+        return _isa.sme_f32f32;
+    }
+    bool has_sme_b16f32() const
+    {
+        return _isa.sme_b16f32;
+    }
     bool has_fp16() const
     {
         return _isa.fp16;
diff --git a/src/common/cpuinfo/CpuIsaInfo.cpp b/src/common/cpuinfo/CpuIsaInfo.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, 2024-2025 Arm Limited.
+ * Copyright (c) 2021-2022, 2024-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -32,20 +32,24 @@
 #define ARM_COMPUTE_CPU_FEATURE_HWCAP_NEON (1 << 12)
 
 /* Arm64 Feature flags */
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMD     (1 << 1)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_FPHP      (1 << 9)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDHP   (1 << 10)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP   (1 << 20)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_SVE       (1 << 22)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDFHM  (1 << 23)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVE2     (1 << 1)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM  (1 << 9)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEF32MM (1 << 10)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16  (1 << 12)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM     (1 << 13)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_BF16     (1 << 14)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME      (1 << 23)
-#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME2     (1ULL << 37)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMD       (1 << 1)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_FPHP        (1 << 9)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDHP     (1 << 10)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP     (1 << 20)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_SVE         (1 << 22)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDFHM    (1 << 23)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVE2       (1 << 1)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM    (1 << 9)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEF32MM   (1 << 10)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16    (1 << 12)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM       (1 << 13)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_BF16       (1 << 14)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME        (1 << 23)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME_I8I32  (1 << 26)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME_F16F32 (1 << 27)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME_B16F32 (1 << 28)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME_F32F32 (1 << 29)
+#define ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME2       (1ULL << 37)
 
 namespace arm_compute
 {
@@ -84,10 +88,14 @@ void decode_hwcaps(CpuIsaInfo &isa, const uint64_t hwcaps, const uint64_t hwcaps
     isa.svebf16 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16);
 
     // Instruction extensions
-    isa.dot      = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP);
-    isa.i8mm     = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM);
-    isa.svei8mm  = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM);
-    isa.svef32mm = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEF32MM);
+    isa.dot        = is_feature_supported(hwcaps, ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP);
+    isa.i8mm       = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM);
+    isa.sme_b16f32 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME_B16F32);
+    isa.sme_f16f32 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME_F16F32);
+    isa.sme_f32f32 = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME_F32F32);
+    isa.sme_i8i32  = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SME_I8I32);
+    isa.svei8mm    = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM);
+    isa.svef32mm   = is_feature_supported(hwcaps2, ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEF32MM);
 }
 #else  /* defined(__aarch64__) */
 void decode_hwcaps(CpuIsaInfo &isa, const uint64_t hwcaps, const uint64_t hwcaps2)
@@ -101,7 +109,8 @@ void decode_regs(CpuIsaInfo    &isa,
                  const uint64_t isar1,
                  const uint64_t pfr0,
                  const uint64_t pfr1,
-                 const uint64_t svefr0)
+                 const uint64_t svefr0,
+                 const uint64_t smefr0)
 {
     auto is_supported = [](uint64_t feature_reg, uint8_t feature_pos) -> bool
     { return ((feature_reg >> feature_pos) & 0xf); };
@@ -124,6 +133,12 @@ void decode_regs(CpuIsaInfo    &isa,
     isa.i8mm     = is_supported(isar1, 48);
     isa.svei8mm  = is_supported(svefr0, 44);
     isa.svef32mm = is_supported(svefr0, 52);
+
+    // SME features
+    isa.sme_b16f32 = (smefr0 & (1ULL << 34));
+    isa.sme_f16f32 = (smefr0 & (1ULL << 35));
+    isa.sme_f32f32 = (smefr0 & (1ULL << 32));
+    isa.sme_i8i32  = (((smefr0 >> 36) & 0xF) == 0xF);
 }
 
 /** Handle features from allow-listed models in case of problematic kernels
@@ -156,12 +171,12 @@ CpuIsaInfo init_cpu_isa_from_hwcaps(uint64_t hwcaps, uint64_t hwcaps2, uint32_t
     return isa;
 }
 
-CpuIsaInfo
-init_cpu_isa_from_regs(uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t midr)
+CpuIsaInfo init_cpu_isa_from_regs(
+    uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t smefr0, uint64_t midr)
 {
     CpuIsaInfo isa;
 
-    decode_regs(isa, isar0, isar1, pfr0, pfr1, svefr0);
+    decode_regs(isa, isar0, isar1, pfr0, pfr1, svefr0, smefr0);
 
     const CpuModel model = midr_to_model(midr);
     allowlisted_model_features(isa, model);
diff --git a/src/common/cpuinfo/CpuIsaInfo.h b/src/common/cpuinfo/CpuIsaInfo.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, 2024-2025 Arm Limited.
+ * Copyright (c) 2021-2022, 2024-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -52,6 +52,10 @@ struct CpuIsaInfo
     /* Instruction support */
     bool dot{false};
     bool i8mm{false};
+    bool sme_b16f32{false};
+    bool sme_f16f32{false};
+    bool sme_f32f32{false};
+    bool sme_i8i32{false};
     bool svei8mm{false};
     bool svef32mm{false};
 };
@@ -73,12 +77,13 @@ CpuIsaInfo init_cpu_isa_from_hwcaps(uint64_t hwcaps, uint64_t hwcaps2, uint32_t
  * @param[in] pfr0   Value of Processor Feature Register 0 (ID_AA64PFR0_EL1)
  * @param[in] pfr1   Value of Processor Feature Register 1 (ID_AA64PFR1_EL1)
  * @param[in] svefr0 Value of SVE feature ID register 0 (ID_AA64ZFR0_EL1)
+ * @param[in] smefr0 Value of SME feature ID register 0 (ID_AA64SMFR0_EL1)
  * @param[in] midr   Value of Main ID Register (MIDR)
  *
  * @return CpuIsaInfo A populated ISA feature structure
  */
-CpuIsaInfo
-init_cpu_isa_from_regs(uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t midr);
+CpuIsaInfo init_cpu_isa_from_regs(
+    uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t smefr0, uint64_t midr);
 } // namespace cpuinfo
 } // namespace arm_compute
 
diff --git a/src/core/CPP/CPPTypes.cpp b/src/core/CPP/CPPTypes.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022, 2024-2025 Arm Limited.
+ * Copyright (c) 2018-2022, 2024-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -117,6 +117,26 @@ bool CPUInfo::has_sme2() const
     return _impl->info.has_sme2();
 }
 
+bool CPUInfo::has_sme_i8i32() const
+{
+    return _impl->info.has_sme_i8i32();
+}
+
+bool CPUInfo::has_sme_f16f32() const
+{
+    return _impl->info.has_sme_f16f32();
+}
+
+bool CPUInfo::has_sme_f32f32() const
+{
+    return _impl->info.has_sme_f32f32();
+}
+
+bool CPUInfo::has_sme_b16f32() const
+{
+    return _impl->info.has_sme_b16f32();
+}
+
 CPUModel CPUInfo::get_cpu_model() const
 {
     return _impl->info.cpu_model();
diff --git a/tests/main.cpp b/tests/main.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2025 Arm Limited.
+ * Copyright (c) 2017-2026 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -253,6 +253,10 @@ int main(int argc, char **argv)
                 p->print_entry("cpu_has_svei8mm", support::cpp11::to_string(cpu_info.has_svei8mm()));
                 p->print_entry("cpu_has_svebf16", support::cpp11::to_string(cpu_info.has_svebf16()));
                 p->print_entry("cpu_has_sme", support::cpp11::to_string(cpu_info.has_sme()));
+                p->print_entry("cpu_has_sme_f32f32", support::cpp11::to_string(cpu_info.has_sme_f32f32()));
+                p->print_entry("cpu_has_sme_f16f32", support::cpp11::to_string(cpu_info.has_sme_f16f32()));
+                p->print_entry("cpu_has_sme_b16f32", support::cpp11::to_string(cpu_info.has_sme_b16f32()));
+                p->print_entry("cpu_has_sme_i8i32", support::cpp11::to_string(cpu_info.has_sme_i8i32()));
                 p->print_entry("cpu_has_sme2", support::cpp11::to_string(cpu_info.has_sme2()));
                 p->print_entry("cpu_has_fp16", support::cpp11::to_string(cpu_info.has_fp16()));
                 p->print_entry("cpu_has_bf16", support::cpp11::to_string(cpu_info.has_bf16()));

Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,5 @@`
`1`	`1`	`/*`
`2`		`- * Copyright (c) 2021-2022, 2024-2025 Arm Limited.`
	`2`	`+ * Copyright (c) 2021-2022, 2024-2026 Arm Limited.`
`3`	`3`	`*`
`4`	`4`	`* SPDX-License-Identifier: MIT`
`5`	`5`	`*`
`@@ -83,6 +83,22 @@ class CpuInfo`
`83`	`83`	`{`
`84`	`84`	`return _isa.sme2;`
`85`	`85`	`}`
	`86`	`+ bool has_sme_i8i32() const`
	`87`	`+ {`
	`88`	`+ return _isa.sme_i8i32;`
	`89`	`+ }`
	`90`	`+ bool has_sme_f16f32() const`
	`91`	`+ {`
	`92`	`+ return _isa.sme_f16f32;`
	`93`	`+ }`
	`94`	`+ bool has_sme_f32f32() const`
	`95`	`+ {`
	`96`	`+ return _isa.sme_f32f32;`
	`97`	`+ }`
	`98`	`+ bool has_sme_b16f32() const`
	`99`	`+ {`
	`100`	`+ return _isa.sme_b16f32;`
	`101`	`+ }`
`86`	`102`	`bool has_fp16() const`
`87`	`103`	`{`
`88`	`104`	`return _isa.fp16;`