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Redesign atomic store with hints intrinsics (#432)
This proposal is about redesigning atomic store with hint intrinsics, to make them more easily extensible. Checklist: (mark with ``X`` those which apply) * [ ] If an issue reporting the bug exists, I have mentioned it in the PR (do not bother creating the issue if all you want to do is fixing the bug yourself). * [x ] I have added/updated the `SPDX-FileCopyrightText` lines on top of any file I have edited. Format is `SPDX-FileCopyrightText: Copyright {year} {entity or name} <{contact informations}>` (Please update existing copyright lines if applicable. You can specify year ranges with hyphen , as in `2017-2019`, and use commas to separate gaps, as in `2018-2020, 2022`). * [ x] I have updated the `Copyright` section of the sources of the specification I have edited (this will show up in the text rendered in the PDF and other output format supported). The format is the same described in the previous item. * [ ] I have run the CI scripts (if applicable, as they might be tricky to set up on non-*nix machines). The sequence can be found in the [contribution guidelines](https://github.com/ARM-software/acle/blob/main/CONTRIBUTING.md#continuous-integration). Don't worry if you cannot run these scripts on your machine, your patch will be automatically checked in the Actions of the pull request. * [x ] I have added an item that describes the changes I have introduced in this PR in the section **Changes for next release** of the section **Change Control**/**Document history** of the document. Create **Changes for next release** if it does not exist. Notice that changes that are not modifying the content and rendering of the specifications (both HTML and PDF) do not need to be listed. * [ x] When modifying content and/or its rendering, I have checked the correctness of the result in the PDF output (please refer to the instructions on [how to build the PDFs locally](https://github.com/ARM-software/acle/blob/main/CONTRIBUTING.md#continuous-integration)). * [ x] The variable `draftversion` is set to `true` in the YAML header of the sources of the specifications I have modified. * [ ] Please *DO NOT* add my GitHub profile to the list of contributors in the [README](https://github.com/ARM-software/acle/blob/main/README.md#contributors-) page of the project.
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---
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<!--
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SPDX-FileCopyrightText: Copyright 2011-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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SPDX-FileCopyrightText: Copyright 2011-2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
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SPDX-FileCopyrightText: Copyright 2022 Google LLC.
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CC-BY-SA-4.0 AND Apache-Patent-License
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See LICENSE.md file for details
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## Copyright
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* Copyright 2011-2024 Arm Limited and/or its affiliates <open-source-office@arm.com>.
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* Copyright 2011-2026 Arm Limited and/or its affiliates <open-source-office@arm.com>.
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* Copyright 2022 Google LLC.
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## About this document
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* Removed all references to Transactional Memory Extension (TME).
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* Added [**Alpha**](#current-status-and-anticipated-changes) support
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for Brain 16-bit floating-point vector multiplication intrinsics.
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* Redesigned atomic store with hints intrinsics.
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### References
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`value.val[0]` with the contents of the `ACCDATA_EL1` system register.
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The returned value is the same as for `__arm_st64bv`.
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## Atomic store with PCDPHINT intrinsics
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## Atomic store with hints intrinsics
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This intrinsic provides an atomic store, which will
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make use of the `STSHH` hint instruction immediately followed by the
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associated store instruction. This intrinsic is type generic and
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supports scalar types from 8-64 bits and is available when
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`__ARM_FEATURE_PCDPHINT` is defined.
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This intrinsic provides an atomic store together with a hint value.
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The hint is a suggestion to the compiler and maps directly to a
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specific hint instruction variant in the ISA. The compiler may use this hint
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when selecting code sequences, but it is not required to emit a specific
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hint instruction or a specific instruction sequence. This intrinsic is
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type generic and supports scalar integral and floating-point types of 8, 16, 32, and 64 bits.
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To access this intrinsic, `<arm_acle.h>` should be included.
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``` c
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void __arm_atomic_store_with_stshh(type *ptr,
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type data,
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int memory_order,
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int ret); /* Retention Policy */
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void __arm_atomic_store_with_hint(type *ptr,
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type data,
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int memory_order,
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int hint);
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```
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The first argument in this intrinsic is a pointer `ptr` which is the location to store to.
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The second argument `data` is the data which is to be stored.
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The third argument `mem` can be one of 3 memory ordering variables supported by atomic_store:
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__ATOMIC_RELAXED, __ATOMIC_SEQ_CST, and __ATOMIC_RELEASE.
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The fourth argument can contain the following values:
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The first argument `ptr` is the location to store to. The second
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argument `data` is the value to be stored. The third argument
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`memory_order` can be one of the memory ordering values supported by
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`atomic_store`: `__ATOMIC_RELAXED`, `__ATOMIC_SEQ_CST`, and
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`__ATOMIC_RELEASE`.
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| **Retention Policy** | **Value** | **Summary** |
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| -------------------- | --------- | --------------------------------------------------------------------------------- |
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| KEEP | 0 | Signals to retain the updated location in the local cache of the updating PE. |
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| STRM | 1 | Signals to not retain the updated location in the local cache of the updating PE. |
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The fourth argument `hint` selects the requested hint. The set of valid
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hint values depends on the architectural features supported by the
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target. The following hint values are defined:
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| **Hint** | **Value** | **Feature** | **Summary** |
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| ---------------- | --------- | -------------------------- | --------------------------------------------------------------------------------- |
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| HINT_STSHH_KEEP | 0 | `__ARM_FEATURE_PCDPHINT` | Requests retention of the updated location in the local cache of the updating PE. |
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| HINT_STSHH_STRM | 1 | `__ARM_FEATURE_PCDPHINT` | Requests that the updated location not be retained in the local cache of the updating PE. |
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# Custom Datapath Extension
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