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1 parent 6d516b9 commit cc85c26Copy full SHA for cc85c26
1 file changed
hwcomponents_library/library/misc.py
@@ -172,6 +172,7 @@ def __init__(
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n_banks: int = 1,
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):
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self.sram: SRAM = SRAM(
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+ size=size,
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tech_node=tech_node,
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width=width,
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depth=depth,
@@ -181,6 +182,7 @@ def __init__(
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# Use the SRAM's width, depth, and size because it does validation for us
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width = self.sram.width
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depth = self.sram.depth
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+ size = self.sram.size
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self.address_bits = max(math.ceil(math.log2(depth)), 1)
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self.width = width
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