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| 1 | +------------------------------------------------------------------------------ |
| 2 | +-- -- |
| 3 | +-- Copyright (C) 2017, AdaCore -- |
| 4 | +-- -- |
| 5 | +-- Redistribution and use in source and binary forms, with or without -- |
| 6 | +-- modification, are permitted provided that the following conditions are -- |
| 7 | +-- met: -- |
| 8 | +-- 1. Redistributions of source code must retain the above copyright -- |
| 9 | +-- notice, this list of conditions and the following disclaimer. -- |
| 10 | +-- 2. Redistributions in binary form must reproduce the above copyright -- |
| 11 | +-- notice, this list of conditions and the following disclaimer in -- |
| 12 | +-- the documentation and/or other materials provided with the -- |
| 13 | +-- distribution. -- |
| 14 | +-- 3. Neither the name of the copyright holder nor the names of its -- |
| 15 | +-- contributors may be used to endorse or promote products derived -- |
| 16 | +-- from this software without specific prior written permission. -- |
| 17 | +-- -- |
| 18 | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- |
| 19 | +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- |
| 20 | +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- |
| 21 | +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- |
| 22 | +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- |
| 23 | +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- |
| 24 | +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- |
| 25 | +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- |
| 26 | +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
| 27 | +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- |
| 28 | +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- |
| 29 | +-- -- |
| 30 | +------------------------------------------------------------------------------ |
| 31 | + |
| 32 | +-- A driver for the Cyclic Redundancy Check CRC-32 calculation processor, |
| 33 | +-- using DMA to transfer the data to the CRC unit (instead of the CPU). |
| 34 | + |
| 35 | +-- Note this API is for the STM32 F4x family. Other STM MCUs have additional |
| 36 | +-- CRC capabilities. |
| 37 | + |
| 38 | +-- See also app note AN4187 "Using CRC through DMA" |
| 39 | + |
| 40 | +-- Example usage, assuming prior clock enabling for the CRC unit: |
| 41 | + |
| 42 | +-- Checksum_DMA : UInt32 := 0; |
| 43 | +-- |
| 44 | +-- Data : constant Block_32 := ( .... ); |
| 45 | +-- |
| 46 | +-- ... |
| 47 | +-- |
| 48 | +-- Enable_Clock (Controller); |
| 49 | +-- |
| 50 | +-- Reset (Controller); |
| 51 | +-- |
| 52 | +-- Reset_Calculator (CRC_Unit); -- if need be |
| 53 | +-- |
| 54 | +-- Update_CRC (CRC_Unit, Controller'Access, Stream, Input => Data); |
| 55 | +-- |
| 56 | +-- DMA_IRQ_Handler.Await_Event (Next_DMA_Interrupt); |
| 57 | +-- |
| 58 | +-- if Next_DMA_Interrupt /= Transfer_Complete_Interrupt then |
| 59 | +-- Panic; |
| 60 | +-- end if; |
| 61 | +-- |
| 62 | +-- Checksum_DMA := Value (CRC_Unit); |
| 63 | + |
| 64 | +with STM32.DMA; use STM32.DMA; |
| 65 | +with System; |
| 66 | + |
| 67 | +package STM32.CRC.DMA is |
| 68 | + pragma Elaborate_Body; |
| 69 | + |
| 70 | + -- These routines use the specified controller and stream to transfer |
| 71 | + -- all of the Input data components to This CRC unit, updating the |
| 72 | + -- CRC value accordingly. At the end of the transfer the DMA interrupt |
| 73 | + -- Transfer_Complete_Interrupt is triggered. Clients are expected to have |
| 74 | + -- an application-defined handler for that interrupt, in order to await |
| 75 | + -- completion of the transfer. |
| 76 | + |
| 77 | + -- These routines can be called multiple times, back-to-back, presumably |
| 78 | + -- with different input blocks, in order to update the value of the |
| 79 | + -- calculated CRC checksum within the CRC processor. Each call will |
| 80 | + -- result in a Transfer_Complete_Interrupt event. |
| 81 | + |
| 82 | + -- Note that you can use a slice if the entire block is not intended for |
| 83 | + -- transfer, but beware alignment boundaries to prevent copying of the |
| 84 | + -- actual parameter into a temporary. |
| 85 | + |
| 86 | + procedure Update_CRC |
| 87 | + (This : in out CRC_32; |
| 88 | + Controller : access DMA_Controller; |
| 89 | + Stream : DMA_Stream_Selector; |
| 90 | + Input : Block_32); |
| 91 | + -- Update the calculated CRC value based on all of the 32-bit components |
| 92 | + -- of Input. Triggers the Transfer_Complete_Interrupt on completion. |
| 93 | + |
| 94 | + procedure Update_CRC |
| 95 | + (This : in out CRC_32; |
| 96 | + Controller : access DMA_Controller; |
| 97 | + Stream : DMA_Stream_Selector; |
| 98 | + Input : Block_16); |
| 99 | + -- Update the calculated CRC value based on all of the 16-bit components |
| 100 | + -- of Input. Triggers the Transfer_Complete_Interrupt on completion. |
| 101 | + |
| 102 | + procedure Update_CRC |
| 103 | + (This : in out CRC_32; |
| 104 | + Controller : access DMA_Controller; |
| 105 | + Stream : DMA_Stream_Selector; |
| 106 | + Input : Block_8); |
| 107 | + -- Update the calculated CRC value based on all of the 8-bit components |
| 108 | + -- of Input. Triggers the Transfer_Complete_Interrupt on completion. |
| 109 | + |
| 110 | +private |
| 111 | + |
| 112 | + procedure Transfer_Input_To_CRC |
| 113 | + (This : in out CRC_32; |
| 114 | + Controller : access DMA_Controller; |
| 115 | + Stream : DMA_Stream_Selector; |
| 116 | + Input_Address : System.Address; |
| 117 | + Input_Length : UInt16; |
| 118 | + Data_Width : DMA_Data_Transfer_Widths); |
| 119 | + -- Configures the DMA controller and stream for transfering memory blocks, |
| 120 | + -- of the width specified by Data_Width, to This CRC processor. Then uses |
| 121 | + -- the controller and stream to transfer the data starting at Input_Address |
| 122 | + -- to This CRC unit, updating the CRC value accordingly. The number of |
| 123 | + -- Input memory items (of Data_Width size) to be transferred is specified |
| 124 | + -- by Input_Length. At the end of the transfer the DMA interrupt |
| 125 | + -- Transfer_Complete_Interrupt is triggered. |
| 126 | + |
| 127 | +end STM32.CRC.DMA; |
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