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| 1 | +------------------------------------------------------------------------------ |
| 2 | +-- -- |
| 3 | +-- Copyright (C) 2026, AdaCore -- |
| 4 | +-- -- |
| 5 | +-- Redistribution and use in source and binary forms, with or without -- |
| 6 | +-- modification, are permitted provided that the following conditions are -- |
| 7 | +-- met: -- |
| 8 | +-- 1. Redistributions of source code must retain the above copyright -- |
| 9 | +-- notice, this list of conditions and the following disclaimer. -- |
| 10 | +-- 2. Redistributions in binary form must reproduce the above copyright -- |
| 11 | +-- notice, this list of conditions and the following disclaimer in -- |
| 12 | +-- the documentation and/or other materials provided with the -- |
| 13 | +-- distribution. -- |
| 14 | +-- 3. Neither the name of the copyright holder nor the names of its -- |
| 15 | +-- contributors may be used to endorse or promote products derived -- |
| 16 | +-- from this software without specific prior written permission. -- |
| 17 | +-- -- |
| 18 | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- |
| 19 | +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- |
| 20 | +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- |
| 21 | +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- |
| 22 | +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- |
| 23 | +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- |
| 24 | +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- |
| 25 | +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- |
| 26 | +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
| 27 | +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- |
| 28 | +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- |
| 29 | +-- -- |
| 30 | +------------------------------------------------------------------------------ |
| 31 | + |
| 32 | +-- This package provides subprograms to configure the Memory Protection |
| 33 | +-- Unit (MPU) on the Cortex-M7 family of CPU. |
| 34 | +-- |
| 35 | +-- On Cortex-M7, the MPU is required when the D-cache is enabled in order |
| 36 | +-- to prevent speculative reads from causing bus contention on external |
| 37 | +-- memory interfaces (e.g., FMC/SDRAM). Without MPU configuration, the |
| 38 | +-- default memory map treats all external memory as Normal, allowing the |
| 39 | +-- CPU to issue speculative reads that can starve bus masters such as the |
| 40 | +-- LTDC display controller. |
| 41 | + |
| 42 | +with HAL; |
| 43 | +with System; |
| 44 | + |
| 45 | +package Cortex_M.MPU is |
| 46 | + |
| 47 | + type Region_Number is range 0 .. 7; |
| 48 | + |
| 49 | + type Region_Size is |
| 50 | + (Size_32B, Size_64B, Size_128B, Size_256B, |
| 51 | + Size_512B, Size_1KB, Size_2KB, Size_4KB, |
| 52 | + Size_8KB, Size_16KB, Size_32KB, Size_64KB, |
| 53 | + Size_128KB, Size_256KB, Size_512KB, Size_1MB, |
| 54 | + Size_2MB, Size_4MB, Size_8MB, Size_16MB, |
| 55 | + Size_32MB, Size_64MB, Size_128MB, Size_256MB, |
| 56 | + Size_512MB, Size_1GB, Size_2GB, Size_4GB); |
| 57 | + |
| 58 | + for Region_Size use |
| 59 | + (Size_32B => 16#04#, Size_64B => 16#05#, |
| 60 | + Size_128B => 16#06#, Size_256B => 16#07#, |
| 61 | + Size_512B => 16#08#, Size_1KB => 16#09#, |
| 62 | + Size_2KB => 16#0A#, Size_4KB => 16#0B#, |
| 63 | + Size_8KB => 16#0C#, Size_16KB => 16#0D#, |
| 64 | + Size_32KB => 16#0E#, Size_64KB => 16#0F#, |
| 65 | + Size_128KB => 16#10#, Size_256KB => 16#11#, |
| 66 | + Size_512KB => 16#12#, Size_1MB => 16#13#, |
| 67 | + Size_2MB => 16#14#, Size_4MB => 16#15#, |
| 68 | + Size_8MB => 16#16#, Size_16MB => 16#17#, |
| 69 | + Size_32MB => 16#18#, Size_64MB => 16#19#, |
| 70 | + Size_128MB => 16#1A#, Size_256MB => 16#1B#, |
| 71 | + Size_512MB => 16#1C#, Size_1GB => 16#1D#, |
| 72 | + Size_2GB => 16#1E#, Size_4GB => 16#1F#); |
| 73 | + |
| 74 | + type Access_Permission is |
| 75 | + (No_Access, |
| 76 | + Privileged_RW, |
| 77 | + Privileged_RW_Unprivileged_RO, |
| 78 | + Full_Access, |
| 79 | + Privileged_RO, |
| 80 | + Privileged_RO_Unprivileged_RO); |
| 81 | + |
| 82 | + for Access_Permission use |
| 83 | + (No_Access => 0, |
| 84 | + Privileged_RW => 1, |
| 85 | + Privileged_RW_Unprivileged_RO => 2, |
| 86 | + Full_Access => 3, |
| 87 | + Privileged_RO => 5, |
| 88 | + Privileged_RO_Unprivileged_RO => 6); |
| 89 | + |
| 90 | + subtype TEX_Level is HAL.UInt3; |
| 91 | + |
| 92 | + subtype Subregion_Disable is HAL.UInt8; |
| 93 | + |
| 94 | + type Region_Configuration is record |
| 95 | + Number : Region_Number; |
| 96 | + Base_Address : System.Address; |
| 97 | + Size : Region_Size; |
| 98 | + Subregion_Disable : MPU.Subregion_Disable := 16#00#; |
| 99 | + TEX : TEX_Level := 0; |
| 100 | + Access_Permission : MPU.Access_Permission := Full_Access; |
| 101 | + Execute_Never : Boolean := False; |
| 102 | + Shareable : Boolean := False; |
| 103 | + Cacheable : Boolean := False; |
| 104 | + Bufferable : Boolean := False; |
| 105 | + end record; |
| 106 | + |
| 107 | + -- Enable/disable control bits for HAL_MPU_Enable |
| 108 | + type MPU_Control is record |
| 109 | + Hard_Fault_NMI_Enable : Boolean; |
| 110 | + -- When True, the MPU is enabled during hard fault, NMI, and FAULTMASK |
| 111 | + Privileged_Default : Boolean; |
| 112 | + -- When True, enables the default memory map as a background region |
| 113 | + -- for privileged access |
| 114 | + end record; |
| 115 | + |
| 116 | + procedure Enable (Control : MPU_Control); |
| 117 | + -- Enable the MPU with the specified control options. |
| 118 | + -- DSB and ISB are issued after enabling. |
| 119 | + |
| 120 | + procedure Disable; |
| 121 | + -- Disable the MPU. DSB and ISB are issued after disabling. |
| 122 | + |
| 123 | + procedure Configure_Region (Config : Region_Configuration); |
| 124 | + -- Configure a single MPU region. The region is enabled upon return. |
| 125 | + |
| 126 | + procedure Disable_Region (Number : Region_Number); |
| 127 | + -- Disable a single MPU region. |
| 128 | + |
| 129 | +end Cortex_M.MPU; |
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