Add ISB to Memory_Barriers for sake of completeness#463
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pat-rogers wants to merge 19 commits intoAdaCore:masterfrom
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Add ISB to Memory_Barriers for sake of completeness#463pat-rogers wants to merge 19 commits intoAdaCore:masterfrom
pat-rogers wants to merge 19 commits intoAdaCore:masterfrom
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* Document the fact (in comments) that the "Errata work-arounds" are completely mysterious. * update copyright year * Add comment for entire unit at top
Otherwise, as a range constraint, the result would be order-dependent on the parent type. Now use No_Output for the default value of the Output record component, to check for lack of a prior call to Initialize.
* for the Ethernet MAC frame filter register, ie MACFFR_Register, correct a component name, a type, and a size in MACFFR_Register to match the documentation. Component "RAM" should be "PAM", and PCF should be a 2-bit quantity (requiring a change to the size of the unused bits reserved at the end) * for the Ethernet MAC debug register, ie MACDBGR_Register, the package from SVD does not correspond to the documentation at all. Therefore we change this register definition manually. See RM0385 Rev 8 pages 1610 and 1611. * likewise, for the Ethernet MAC MII data register, ie MACMIIDR_Register, change component name to match documentation We also need to change the SVD file itself, in the svd2ada project.
* Change ADT name to Audio_CODEC for closer match to documentation and meaningfulness * For the same reasons, change name Output_Device to Analog_Outputs. * Minor reordering to put the primary ADT declaration near the top of the package.
The generic Cache_Maintenance procedure used the raw Start address as the initial DCCMVAC write address without first aligning it down to a cache line boundary. If Start was not 32-byte aligned, the first cache line was only partially cleaned. Additionally, Len was not extended to account for the trimmed prefix bytes, leaving the final partial cache line unflushed. Fix by aligning Op_Addr down to the nearest cache line boundary and extending Op_Size by the corresponding offset, ensuring all cache lines covering [Start, Start+Len) are cleaned. correct new copyright date formatting for readability
Affects: stm32-dma2d_bitmap, framebuffer_ltdc DMA2D_Fill_Rect was called without Synchronous => True, allowing DMA2D writes to the hidden framebuffer to still be in progress when Internal_Update_Layer flushed and handed the buffer to LTDC. Fix Fill_Rect to use Synchronous => True, consistent with Fill. Add Clean_DCache in Internal_Update_Layer covering the hidden buffer before Set_Frame_Buffer, ensuring CPU-written dirty cache lines are flushed to physical memory before LTDC DMA reads them. Add comments explaining the approach to the cache in Internal_Update_Layer
We now compute them from the datasheet constants. Specifically, in procedure Initialize: * ExitSelfRefreshDelay, SelfRefreshTime, and RowCycleDelay were all derived from a single SDRAM_Min_Delay_In_ns constant, collapsing three distinct timing constraints (TXSR, TRAS, TRC) into one value. SelfRefreshTime was also hardcoded to 4 cycles, valid only at 90 MHz SDCLK. * Replace with per-parameter ceiling division over named board constants (SDRAM_TXSR_In_Ns, SDRAM_TRAS_In_Ns, SDRAM_TRC_In_Ns) so each constraint is satisfied independently at any clock frequency. STM32.Board spec: * add new SDRAM constants for the sake of the SDRAM initialization
* add new declarations for Ethernet Physical Layer I/O Pins * add new procedures for enabling RMII clocks and pins
correct letter casing fix words changed in comments due to refactoring
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And mark both routines as Inline_Always. Note that is a change for DSB which was just marked Inline, but these don't make sense when not inline.