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Add ISB to Memory_Barriers for sake of completeness #463

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623b50b
adding/revising WM8994 driver and Audio wrapper driver for it
Mar 27, 2024
9915162
use new IO package for WM8994, with constants for register addresses
Mar 27, 2024
a660c65
better name for procedure Play
Mar 28, 2024
264a39b
Move to signed 16-bit PCM samples, rather than unsigned
Mar 28, 2024
b72118a
Add important comments re: mystery code and update copyright year
Mar 28, 2024
5b05320
Make the output device type use a static predicate to limit the options
Mar 28, 2024
01a1064
Add support for dual channel conversion
pat-rogers Mar 21, 2026
1403b9f
replace curly quotes with straight quotes in comments for sake of co…
pat-rogers Mar 21, 2026
d8722c4
Correct ethernet registers' decls due to incorrect SVD file.
pat-rogers Mar 21, 2026
9e05522
Change type names to match WM8994 datasheet.
pat-rogers Mar 21, 2026
60c8961
Fix cache line alignment in Cache_Maintenance
pat-rogers Mar 21, 2026
2f7d2eb
Fix potential display coherency problem when D-cache is enabled
pat-rogers Mar 21, 2026
e989884
use new name for WM8994_Audio_Device
pat-rogers Mar 23, 2026
2f42a0c
Fix SDRAM timing setup parameters
pat-rogers Mar 24, 2026
c67fae2
Add support for Ethernet RMII
pat-rogers Mar 23, 2026
958113c
change procedure name Start_Playing back to Play
pat-rogers Mar 23, 2026
117523a
use a "private with" for Ravenscar_Time
pat-rogers Mar 24, 2026
2acf46c
new general MPU config facility; also fixes LTDC slew
pat-rogers Mar 28, 2026
85c8e48
Add ISB for completeness
pat-rogers Apr 6, 2026
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10 changes: 5 additions & 5 deletions arch/ARM/STM32/drivers/sai/stm32-sai.ads
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
------------------------------------------------------------------------------
-- --
-- Copyright (C) 2016, AdaCore --
-- Copyright (C) 2016-2026, AdaCore --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions are --
Expand Down Expand Up @@ -188,7 +188,7 @@ package STM32.SAI is
(FS_Frame,
FS_Frame_And_Channel_Identification)
with Size => 1;
-- Meaningless and is not used in AC’97 or SPDIF audio block
-- Meaningless and is not used in AC'97 or SPDIF audio block
-- configuration. It must be configured when the audio block is disabled.
--
-- In case of FS_Frame_And_Channel_Identification, the number of slots
Expand All @@ -206,7 +206,7 @@ package STM32.SAI is
FS_Active_High)
with Size => 1;
-- It is used to configure the level of the start of frame on the FS
-- signal. It is meaningless and is not used in AC’97 or SPDIF audio
-- signal. It is meaningless and is not used in AC'97 or SPDIF audio
-- block configuration.
--
-- FS_Active_Low: FS is active low (falling edge)
Expand All @@ -216,7 +216,7 @@ package STM32.SAI is
(First_Bit,
Before_First_Bit)
with Size => 1;
-- Meaningless and is not used in AC’97 or SPDIF audio block
-- Meaningless and is not used in AC'97 or SPDIF audio block
-- configuration. This bit must be configured when the audio block
-- is disabled.
-- First_Bit: FS is asserted on the first bit of the slot 0.
Expand All @@ -231,7 +231,7 @@ package STM32.SAI is
-- The slot size must be higher or equal to the data size. If this
-- condition is not respected, the behavior of the SAI will be
-- undetermined.
-- Ignored in AC’97 or SPDIF mode.
-- Ignored in AC'97 or SPDIF mode.
-- Data_Size: The slot size is equivalent to the data size (specified in
-- DS[3:0] in the SAI_xCR1 register).

Expand Down
89 changes: 67 additions & 22 deletions arch/ARM/STM32/drivers/stm32-dac.adb
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
------------------------------------------------------------------------------
-- --
-- Copyright (C) 2015, AdaCore --
-- Copyright (C) 2015-2026, AdaCore --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions are --
Expand Down Expand Up @@ -115,11 +115,9 @@ package body STM32.DAC is
when DAC_Resolution_12_Bits =>
case Alignment is
when Left_Aligned =>
This.DHR12L1.DACC1DHR :=
UInt12 (Value and Max_12bit_Resolution);
This.DHR12L1.DACC1DHR := UInt12 (Value and Max_12bit_Resolution);
when Right_Aligned =>
This.DHR12R1.DACC1DHR :=
UInt12 (Value and Max_12bit_Resolution);
This.DHR12R1.DACC1DHR := UInt12 (Value and Max_12bit_Resolution);
end case;
when DAC_Resolution_8_Bits =>
This.DHR8R1.DACC1DHR := UInt8 (Value and Max_8bit_Resolution);
Expand All @@ -130,11 +128,9 @@ package body STM32.DAC is
when DAC_Resolution_12_Bits =>
case Alignment is
when Left_Aligned =>
This.DHR12L2.DACC2DHR :=
UInt12 (Value and Max_12bit_Resolution);
This.DHR12L2.DACC2DHR := UInt12 (Value and Max_12bit_Resolution);
when Right_Aligned =>
This.DHR12R2.DACC2DHR :=
UInt12 (Value and Max_12bit_Resolution);
This.DHR12R2.DACC2DHR := UInt12 (Value and Max_12bit_Resolution);
end case;
when DAC_Resolution_8_Bits =>
This.DHR8R2.DACC2DHR := UInt8 (Value and Max_8bit_Resolution);
Expand All @@ -143,6 +139,35 @@ package body STM32.DAC is
end case;
end Set_Output;

-----------------------------
-- Set_Dual_Channel_Output --
-----------------------------

procedure Set_Dual_Channel_Output
(This : in out Digital_To_Analog_Converter;
Channel_2_Data : UInt16;
Channel_1_Data : UInt16;
Resolution : DAC_Resolution;
Alignment : Data_Alignment)
is
begin
-- See RM0385 Rev 8, sections 16.5.9 .. 16.5.11 for these registers
case Resolution is
when DAC_Resolution_12_Bits =>
case Alignment is
when Left_Aligned =>
This.DHR12LD.DACC2DHR := UInt12 (Channel_2_Data and Max_12bit_Resolution);
This.DHR12LD.DACC1DHR := UInt12 (Channel_1_Data and Max_12bit_Resolution);
when Right_Aligned =>
This.DHR12RD.DACC2DHR := UInt12 (Channel_2_Data and Max_12bit_Resolution);
This.DHR12RD.DACC1DHR := UInt12 (Channel_1_Data and Max_12bit_Resolution);
end case;
when DAC_Resolution_8_Bits =>
This.DHR8RD.DACC2DHR := UInt8 (Channel_2_Data and Max_8bit_Resolution);
This.DHR8RD.DACC1DHR := UInt8 (Channel_1_Data and Max_8bit_Resolution);
end case;
end Set_Dual_Channel_Output;

------------------------------------
-- Trigger_Conversion_By_Software --
------------------------------------
Expand Down Expand Up @@ -194,21 +219,15 @@ package body STM32.DAC is
when DAC_Resolution_12_Bits =>
case Alignment is
when Left_Aligned =>
This.DHR12LD.DACC1DHR :=
UInt12 (Channel_1_Value and Max_12bit_Resolution);
This.DHR12LD.DACC2DHR :=
UInt12 (Channel_2_Value and Max_12bit_Resolution);
This.DHR12LD.DACC1DHR := UInt12 (Channel_1_Value and Max_12bit_Resolution);
This.DHR12LD.DACC2DHR := UInt12 (Channel_2_Value and Max_12bit_Resolution);
when Right_Aligned =>
This.DHR12RD.DACC1DHR :=
UInt12 (Channel_1_Value and Max_12bit_Resolution);
This.DHR12RD.DACC2DHR :=
UInt12 (Channel_2_Value and Max_12bit_Resolution);
This.DHR12RD.DACC1DHR := UInt12 (Channel_1_Value and Max_12bit_Resolution);
This.DHR12RD.DACC2DHR := UInt12 (Channel_2_Value and Max_12bit_Resolution);
end case;
when DAC_Resolution_8_Bits =>
This.DHR8RD.DACC1DHR :=
UInt8 (Channel_1_Value and Max_8bit_Resolution);
This.DHR8RD.DACC2DHR :=
UInt8 (Channel_2_Value and Max_8bit_Resolution);
This.DHR8RD.DACC1DHR := UInt8 (Channel_1_Value and Max_8bit_Resolution);
This.DHR8RD.DACC2DHR := UInt8 (Channel_2_Value and Max_8bit_Resolution);
end case;
end Set_Dual_Output_Voltages;

Expand Down Expand Up @@ -682,10 +701,36 @@ package body STM32.DAC is
when DAC_Resolution_8_Bits =>
Result := This.DHR8R2'Address;
end case;

end case;

return Result;
end Data_Address;

----------------------------------
-- Data_Address_Dual_Conversion --
----------------------------------

function Data_Address_Dual_Conversion
(This : Digital_To_Analog_Converter;
Resolution : DAC_Resolution;
Alignment : Data_Alignment)
return Address
is
Result : Address;
begin
case Resolution is
when DAC_Resolution_12_Bits =>
case Alignment is
when Left_Aligned =>
Result := This.DHR12LD'Address;
when Right_Aligned =>
Result := This.DHR12RD'Address;
end case;
when DAC_Resolution_8_Bits =>
Result := This.DHR8RD'Address;
end case;

return Result;
end Data_Address_Dual_Conversion;

end STM32.DAC;
32 changes: 29 additions & 3 deletions arch/ARM/STM32/drivers/stm32-dac.ads
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
------------------------------------------------------------------------------
-- --
-- Copyright (C) 2015, AdaCore --
-- Copyright (C) 2015-2026, AdaCore --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions are --
Expand Down Expand Up @@ -51,7 +51,9 @@ package STM32.DAC is

type DAC_Channel is (Channel_1, Channel_2);

-- Note that Channel 1 is tied to GPIO pin PA4, and Channel 2 to PA5
-- Note that Channel 1 is tied to GPIO pin PA4, and Channel 2 to PA5.
-- Note that Channel 1 is mapped to DMA1 Stream 5 channel 7.
-- Note that Channel 2 is mapped on DMA1 Stream 6 channel 7.

procedure Enable
(This : in out Digital_To_Analog_Converter;
Expand Down Expand Up @@ -88,6 +90,8 @@ package STM32.DAC is
Max_8bit_Resolution : constant := 16#00FF#;

type Data_Alignment is (Left_Aligned, Right_Aligned);
-- These only apply when using 12-bit resolution. For 8-bit resolution the
-- alignment is always right-aligned.

procedure Set_Output
(This : in out Digital_To_Analog_Converter;
Expand All @@ -102,6 +106,18 @@ package STM32.DAC is
-- the reference input voltage and the 'n' of Max_nbit_Counts is either 12
-- or 8.

procedure Set_Dual_Channel_Output
(This : in out Digital_To_Analog_Converter;
Channel_2_Data : UInt16;
Channel_1_Data : UInt16;
Resolution : DAC_Resolution;
Alignment : Data_Alignment);
-- This routine writes the 32-bit value, composed from the two 16-bit
-- values, with the necessary layout (8/12left-right alignment) to
-- the appropriate output register for conversion on both channels
-- simultaneously. DMA is the alternative to software calling this
-- procedure.

procedure Trigger_Conversion_By_Software
(This : in out Digital_To_Analog_Converter;
Channel : DAC_Channel)
Expand Down Expand Up @@ -328,7 +344,17 @@ package STM32.DAC is
Alignment : Data_Alignment)
return Address;
-- Returns the address of the Data Holding register within This, for the
-- specified Channel, at the specified Resolution and Alignment.
-- specified Channel, given the specified Resolution and Alignment.
--
-- This function is stricly for use with DMA, all others use the API above.

function Data_Address_Dual_Conversion
(This : Digital_To_Analog_Converter;
Resolution : DAC_Resolution;
Alignment : Data_Alignment)
return Address;
-- Returns the address of the Data Holding register within This, for the
-- dual conversion case, given the specified Resolution and Alignment.
--
-- This function is stricly for use with DMA, all others use the API above.

Expand Down
85 changes: 51 additions & 34 deletions arch/ARM/STM32/svd/stm32f7x/stm32_svd-ethernet.ads
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Original file line number Diff line number Diff line change
Expand Up @@ -411,19 +411,19 @@ package STM32_SVD.Ethernet is
-- no description available
DAIF : Boolean := False;
-- no description available
RAM : Boolean := False;
PAM : Boolean := False; -- was RAM, incorrectly named in original SVD (see corrected SVD file)
-- no description available
BFD : Boolean := False;
-- no description available
PCF : Boolean := False;
PCF : HAL.UInt2 := 0; -- incorrectly set to 1 bit in original SVD (see corrected SVD file)
-- no description available
SAIF : Boolean := False;
-- no description available
SAF : Boolean := False;
-- no description available
HPF : Boolean := False;
-- unspecified
Reserved_10_30 : HAL.UInt21 := 16#0#;
Reserved_11_30 : HAL.UInt20 := 16#0#; -- incorrectly set to 21 bits in original SVD (see corrected SVD file)
-- no description available
RA : Boolean := False;
end record
Expand All @@ -435,13 +435,13 @@ package STM32_SVD.Ethernet is
HU at 0 range 1 .. 1;
HM at 0 range 2 .. 2;
DAIF at 0 range 3 .. 3;
RAM at 0 range 4 .. 4;
PAM at 0 range 4 .. 4;
BFD at 0 range 5 .. 5;
PCF at 0 range 6 .. 6;
SAIF at 0 range 7 .. 7;
SAF at 0 range 8 .. 8;
HPF at 0 range 9 .. 9;
Reserved_10_30 at 0 range 10 .. 30;
PCF at 0 range 6 .. 7;
SAIF at 0 range 8 .. 8;
SAF at 0 range 9 .. 9;
HPF at 0 range 10 .. 10;
Reserved_11_30 at 0 range 11 .. 30;
RA at 0 range 31 .. 31;
end record;

Expand Down Expand Up @@ -484,15 +484,15 @@ package STM32_SVD.Ethernet is
-- Ethernet MAC MII data register
type MACMIIDR_Register is record
-- no description available
TD : MACMIIDR_TD_Field := 16#0#;
MD : MACMIIDR_TD_Field := 16#0#; -- was TD, incorrectly named in original SVD (see corrected SVD file)
-- unspecified
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Size => 32,
Bit_Order => System.Low_Order_First;

for MACMIIDR_Register use record
TD at 0 range 0 .. 15;
MD at 0 range 0 .. 15;
Reserved_16_31 at 0 range 16 .. 31;
end record;

Expand Down Expand Up @@ -594,34 +594,51 @@ package STM32_SVD.Ethernet is
WFFRPR at 0 range 31 .. 31;
end record;

-- Ethernet MAC debug register
-- Ethernet MAC debug register. The package from SVD does not correspond
-- to the documentation. Therefore we change this register definition
-- manually. See RM0385 Rev 8 pages 1610 and 1611.
-- TODO: update the SVD file so this manual change isn't necessary!
type MACDBGR_Register is record
-- Read-only. CR
CR : Boolean;
-- Read-only. CSR
CSR : Boolean;
-- Read-only. ROR
ROR : Boolean;
-- Read-only. MCF
MCF : Boolean;
-- Read-only. MCP
MCP : Boolean;
-- Read-only. MCFHP
MCFHP : Boolean;
-- unspecified
Reserved_6_31 : HAL.UInt26;
Reserved_26_31 : HAL.UInt6;
Tx_FIFO_Full : Boolean; -- TFF
Tx_FIFO_Not_Empty : Boolean; -- TFNE
Reserved_23 : HAL.Bit := 0;
Tx_FIFO_Write_Active : Boolean; -- TFWA
Tx_FIFO_Read_Status : HAL.UInt2; -- TFRS
MAC_Transmitter_Paused : Boolean; -- MTP
MAC_Transmit_Frame_Controller_Status : HAL.UInt2; -- MTFCS
MAC_MII_Transmit_Engine_Active : Boolean; -- MMTEA
Reserved_10_15 : HAL.UInt6 := 0;
Rx_FIFO_Fill_Level : HAL.UInt2; -- RFFL
Reserved_7 : HAL.Bit := 0;
Rx_FIFO_Read_Controller_Status : HAL.UInt2; -- RFRCS
Rx_FIFO_Write_Controller_Active : Boolean; -- RFWRA
Reserved_3 : HAL.Bit := 0;
MAC_Small_FIFO_RW_Controller_Status : HAL.UInt2; -- MSFRWCS
MAC_MII_Receive_Protocol_Engine_Active : Boolean; -- MMRPEA
end record
with Volatile_Full_Access, Size => 32,
with Volatile_Full_Access,
Size => 32,
Bit_Order => System.Low_Order_First;

for MACDBGR_Register use record
CR at 0 range 0 .. 0;
CSR at 0 range 1 .. 1;
ROR at 0 range 2 .. 2;
MCF at 0 range 3 .. 3;
MCP at 0 range 4 .. 4;
MCFHP at 0 range 5 .. 5;
Reserved_6_31 at 0 range 6 .. 31;
Reserved_26_31 at 0 range 26 .. 31;
Tx_FIFO_Full at 0 range 25 .. 25;
Tx_FIFO_Not_Empty at 0 range 24 .. 24;
Reserved_23 at 0 range 23 .. 23;
Tx_FIFO_Write_Active at 0 range 22 .. 22;
Tx_FIFO_Read_Status at 0 range 20 .. 21;
MAC_Transmitter_Paused at 0 range 19 .. 19;
MAC_Transmit_Frame_Controller_Status at 0 range 17 .. 18;
MAC_MII_Transmit_Engine_Active at 0 range 16 .. 16;
Reserved_10_15 at 0 range 10 .. 15;
Rx_FIFO_Fill_Level at 0 range 8 .. 9;
Reserved_7 at 0 range 7 .. 7;
Rx_FIFO_Read_Controller_Status at 0 range 5 .. 6;
Rx_FIFO_Write_Controller_Active at 0 range 4 .. 4;
Reserved_3 at 0 range 3 .. 3;
MAC_Small_FIFO_RW_Controller_Status at 0 range 1 .. 2;
MAC_MII_Receive_Protocol_Engine_Active at 0 range 0 .. 0;
end record;

-- Ethernet MAC interrupt status register
Expand Down
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