From 1d5b3533a39ec8038b4f3a725f4eb720ca3af18f Mon Sep 17 00:00:00 2001 From: Pat Rogers Date: Mon, 6 Apr 2026 10:06:40 -0500 Subject: [PATCH 1/2] Add ISB for completeness --- arch/ARM/cortex_m/src/memory_barriers.adb | 14 ++++++++++++-- arch/ARM/cortex_m/src/memory_barriers.ads | 10 +++++++--- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/ARM/cortex_m/src/memory_barriers.adb b/arch/ARM/cortex_m/src/memory_barriers.adb index f790ab434..7ae4d5d24 100644 --- a/arch/ARM/cortex_m/src/memory_barriers.adb +++ b/arch/ARM/cortex_m/src/memory_barriers.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2015, AdaCore -- +-- Copyright (C) 2015-2026, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -40,7 +40,17 @@ package body Memory_Barriers is procedure Data_Synchronization_Barrier is pragma Suppress (All_Checks); begin - Asm ("DSB #0xF", Volatile => True); -- 15 is 'Sy", ie "full system" + Asm ("DSB #0xF", Volatile => True); -- 15 is 'Sy", ie "full system" end Data_Synchronization_Barrier; + ----------------------------------------- + -- Instruction_Synchronization_Barrier -- + ----------------------------------------- + + procedure Instruction_Synchronization_Barrier is + pragma Suppress (All_Checks); + begin + Asm ("ISB", Volatile => True); + end Instruction_Synchronization_Barrier; + end Memory_Barriers; diff --git a/arch/ARM/cortex_m/src/memory_barriers.ads b/arch/ARM/cortex_m/src/memory_barriers.ads index 795e1bb44..3738140a9 100644 --- a/arch/ARM/cortex_m/src/memory_barriers.ads +++ b/arch/ARM/cortex_m/src/memory_barriers.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2015, AdaCore -- +-- Copyright (C) 2015-2026, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,14 +29,18 @@ -- -- ------------------------------------------------------------------------------ --- This file provides utility functions for ARM Cortex microcontrollers +-- This unit provides memory barrier routines for ARM Cortex microcontrollers package Memory_Barriers is pragma Preelaborate; - procedure Data_Synchronization_Barrier with Inline; + procedure Data_Synchronization_Barrier with Inline_Always; -- Injects instruction "DSB Sy" i.e., a "full system" domain barrier + procedure Instruction_Synchronization_Barrier with Inline_Always; + -- Injects instruction "ISB" + procedure DSB renames Data_Synchronization_Barrier; + procedure ISB renames Instruction_Synchronization_Barrier; end Memory_Barriers; From 55ea932ce7cad78cd5d6422a0a26adb2497c28a5 Mon Sep 17 00:00:00 2001 From: Pat Rogers Date: Tue, 14 Apr 2026 15:15:05 -0500 Subject: [PATCH 2/2] Trigger CI