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Add ISB to Memory_Barriers for sake of completeness #464

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Add ISB to Memory_Barriers for sake of completeness #464

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1d5b353
Add ISB for completeness
pat-rogers Apr 6, 2026
55ea932
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pat-rogers Apr 14, 2026
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14 changes: 12 additions & 2 deletions arch/ARM/cortex_m/src/memory_barriers.adb
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
------------------------------------------------------------------------------
-- --
-- Copyright (C) 2015, AdaCore --
-- Copyright (C) 2015-2026, AdaCore --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions are --
Expand Down Expand Up @@ -40,7 +40,17 @@ package body Memory_Barriers is
procedure Data_Synchronization_Barrier is
pragma Suppress (All_Checks);
begin
Asm ("DSB #0xF", Volatile => True); -- 15 is 'Sy", ie "full system"
Asm ("DSB #0xF", Volatile => True); -- 15 is 'Sy", ie "full system"
end Data_Synchronization_Barrier;

-----------------------------------------
-- Instruction_Synchronization_Barrier --
-----------------------------------------

procedure Instruction_Synchronization_Barrier is
pragma Suppress (All_Checks);
begin
Asm ("ISB", Volatile => True);
end Instruction_Synchronization_Barrier;

end Memory_Barriers;
10 changes: 7 additions & 3 deletions arch/ARM/cortex_m/src/memory_barriers.ads
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
------------------------------------------------------------------------------
-- --
-- Copyright (C) 2015, AdaCore --
-- Copyright (C) 2015-2026, AdaCore --
-- --
-- Redistribution and use in source and binary forms, with or without --
-- modification, are permitted provided that the following conditions are --
Expand Down Expand Up @@ -29,14 +29,18 @@
-- --
------------------------------------------------------------------------------

-- This file provides utility functions for ARM Cortex microcontrollers
-- This unit provides memory barrier routines for ARM Cortex microcontrollers

package Memory_Barriers is
pragma Preelaborate;

procedure Data_Synchronization_Barrier with Inline;
procedure Data_Synchronization_Barrier with Inline_Always;
-- Injects instruction "DSB Sy" i.e., a "full system" domain barrier

procedure Instruction_Synchronization_Barrier with Inline_Always;
-- Injects instruction "ISB"

procedure DSB renames Data_Synchronization_Barrier;
procedure ISB renames Instruction_Synchronization_Barrier;

end Memory_Barriers;
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