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feat(examples): simd_profile_probe — hardware verification binary
Supports step 1 of the TEST-promotion checklist from .claude/knowledge/td-simd-cpu-dispatch-matrix.md § "TEST verification checklist": "Boot the binary on the silicon and confirm simd_profile() returns the expected variant." The probe prints: - Resolved SimdProfile variant + arch/family flags - Compile-time pinning status (and pinned variant if active) - Every CPUID-derived SimdCaps bit, ticked/unticked - ARM heuristic profile when running on aarch64 - Active compile-time target features (avx512f / avx2) - Per-variant matrix-doc cell summary (terse — matrix is source of truth) - Runs the same pinning_consistency invariant the unit test checks, so a probe deployed on real silicon flags regressions in the cfg cascade. First-hardware results on the build host (Sapphire Rapids): - simd_profile() resolves to SapphireRapids ✓ - amx_tile + amx_bf16 + avx512fp16 all set ✓ - amx_fp16 unset (correctly NOT promoting to GraniteRapids) ✓ - GNR-before-SPR ordering invariant verified end-to-end This is the first end-to-end pass of the e40f3a3 SimdProfile detect chain plus the 5a3a663 cpu-* pinning machinery on real silicon — confirms the dispatch axis is functional, not just doc-checked. Smoke-tested with --features cpu-zen4: probe correctly reports ACTIVE pinning and Zen4Avx512 as the resolved variant, even on SPR silicon (pinning intentionally overrides hardware detection).
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‎examples/simd_profile_probe.rs‎

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//! `simd_profile_probe` — boot-on-silicon diagnostic for the dispatch matrix.
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//!
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//! Step 1 of the TEST-promotion checklist from
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//! `.claude/knowledge/td-simd-cpu-dispatch-matrix.md` § "TEST verification
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//! checklist": *"Boot the binary on the silicon and confirm `simd_profile()`
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//! returns the expected variant."*
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//!
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//! Prints every CPUID-derived capability bit plus the resolved `SimdProfile`
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//! variant. Used to verify silicon → profile mapping when promoting DOC
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//! cells in the dispatch matrix to TEST.
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//!
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//! Usage:
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//! ```sh
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//! # Runtime detection (default — same binary on any silicon):
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//! cargo run --example simd_profile_probe --release
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//!
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//! # Compile-time pinned (the LazyLock is not linked in):
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//! cargo run --example simd_profile_probe --release --features cpu-spr
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//! ```
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use ndarray::hpc::simd_caps::{simd_caps, ArmProfile, SimdCaps};
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use ndarray::hpc::simd_profile::{is_pinned, pinned_profile, simd_profile, SimdProfile};
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fn main() {
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let caps = simd_caps();
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let profile = simd_profile();
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println!("ndarray simd-profile probe");
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println!("==========================");
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println!();
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// ── Dispatch identity ───────────────────────────────────────────
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println!("Resolved profile: {}", profile.name());
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println!(" is_x86: {}", profile.is_x86());
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println!(" is_aarch64: {}", profile.is_aarch64());
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println!(" has_avx512: {}", profile.has_avx512());
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println!(" has_amx: {}", profile.has_amx());
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println!();
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// ── Pinning status ─────────────────────────────────────────────
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println!("Compile-time pinning: {}", if is_pinned() { "ACTIVE" } else { "off (runtime detection)" });
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if let Some(p) = pinned_profile() {
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println!(" Pinned variant: {}", p.name());
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}
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println!();
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// ── Raw capability bits ────────────────────────────────────────
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println!("SimdCaps (raw bits):");
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print_caps(&caps);
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println!();
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// ── ARM-specific sub-profile (heuristic; deployment-pragmatic) ──
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let arm = caps.arm_profile();
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if !matches!(arm, ArmProfile::NotArm) {
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println!("ARM profile (heuristic): {}", arm.name());
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println!(" est. tok/sec: {}", arm.estimated_tok_per_sec());
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println!(" eff. f32 lanes:{}", arm.effective_f32_lanes());
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println!();
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}
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// ── Build configuration ─────────────────────────────────────────
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println!("Build:");
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println!(" target_arch: {}", std::env::consts::ARCH);
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println!(" target_os: {}", std::env::consts::OS);
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#[cfg(target_feature = "avx512f")]
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println!(" -Ctarget-feature avx512f: yes (compile-time)");
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#[cfg(not(target_feature = "avx512f"))]
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println!(" -Ctarget-feature avx512f: no (compile-time)");
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#[cfg(target_feature = "avx2")]
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println!(" -Ctarget-feature avx2: yes (compile-time)");
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#[cfg(not(target_feature = "avx2"))]
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println!(" -Ctarget-feature avx2: no (compile-time)");
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println!();
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// ── TEST promotion guidance ────────────────────────────────────
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println!("Matrix-doc cells affected by this CPU:");
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matrix_cell_summary(profile);
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// Sanity invariant: simd_profile() and pinned_profile() must agree
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// when pinning is active. This is the same check that
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// `pinning_consistency` runs as a unit test; we re-run it here so a
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// probe binary deployed on real silicon flags any future regression
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// in the cfg cascade.
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if let Some(p) = pinned_profile() {
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assert_eq!(
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profile, p,
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"INVARIANT VIOLATION: pinned_profile()={:?} disagrees with simd_profile()={:?}",
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p, profile
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);
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}
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}
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fn print_caps(c: &SimdCaps) {
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let bits: &[(&str, bool)] = &[
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("avx2", c.avx2),
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("avx512f", c.avx512f),
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("avx512bw", c.avx512bw),
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("avx512vl", c.avx512vl),
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("avx512vnni", c.avx512vnni),
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("avx512vbmi", c.avx512vbmi),
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("avx512vpopcntdq", c.avx512vpopcntdq),
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("avx512bf16", c.avx512bf16),
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("avx512fp16", c.avx512fp16),
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("avx512vp2intersect", c.avx512vp2intersect),
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("avxvnniint8", c.avxvnniint8),
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("amx_tile", c.amx_tile),
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("amx_int8", c.amx_int8),
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("amx_bf16", c.amx_bf16),
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("amx_fp16", c.amx_fp16),
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("fma", c.fma),
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("sse41", c.sse41),
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("sse2", c.sse2),
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("neon", c.neon),
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("asimd_dotprod", c.asimd_dotprod),
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("fp16 (arm)", c.fp16),
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("aes", c.aes),
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("sha2", c.sha2),
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("crc32", c.crc32),
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];
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for (name, present) in bits {
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println!(" [{}] {}", if *present { "x" } else { " " }, name);
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}
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}
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fn matrix_cell_summary(p: SimdProfile) {
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// Lifted from `td-simd-cpu-dispatch-matrix.md` § "Master matrix"
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// for each x86 profile. The summary is intentionally terse — the
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// matrix doc is the source of truth and should be consulted before
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// promoting any DOC cell to TEST.
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let summary: &[&str] = match p {
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SimdProfile::GraniteRapids => &[
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"F+CD+VL+DQ+BW+IFMA+VBMI+VBMI2+VNNI+BF16+FP16",
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"VPOPCNTDQ+BITALG+GFNI+VAES+VPCLMUL",
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"AMX-TILE+INT8+BF16+FP16 (FP16 is the GNR discriminator)",
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],
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SimdProfile::SapphireRapids => &[
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"F+CD+VL+DQ+BW+IFMA+VBMI+VBMI2+VNNI+BF16+FP16",
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"VPOPCNTDQ+BITALG+GFNI+VAES+VPCLMUL",
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"AMX-TILE+INT8+BF16 (no AMX-FP16 — that's GNR)",
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],
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SimdProfile::Zen4Avx512 => &[
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"F+CD+VL+DQ+BW+IFMA+VBMI+VBMI2+VNNI+BF16+FP16",
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"No AMX of any kind; 256-bit FPU double-pumped on Zen4, native 512-bit on Zen5",
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],
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SimdProfile::CooperLake => &[
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"F+CD+VL+DQ+BW+VNNI+BF16",
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"No VBMI, no FP16, no AMX — unique 'BF16 without VBMI'",
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],
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SimdProfile::TigerLakeU => &[
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"F+CD+VL+DQ+BW+IFMA+VBMI+VBMI2+VNNI+VP2INTERSECT",
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"VP2INTERSECT is the sole discriminator vs IceLakeSp",
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],
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SimdProfile::IceLakeSp => &[
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"F+CD+VL+DQ+BW+IFMA+VBMI+VBMI2+VNNI",
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"No BF16, no FP16, no AMX, no VP2INTERSECT",
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],
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SimdProfile::CascadeLake => &["F+CD+VL+DQ+BW+VNNI", "First Xeon with VNNI; no VBMI/BF16/FP16/AMX"],
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SimdProfile::SkylakeX => &["F+CD+VL+DQ+BW", "Founding AVX-512 baseline; everything since adds on top"],
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SimdProfile::ArrowLake => &[
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"No AVX-512 (hybrid CPU design)",
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"AVX-VNNI-INT8 + AVX-IFMA + AVX-NE-CONVERT (256-bit / VEX forms)",
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],
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SimdProfile::HaswellAvx2 => &["AVX2 + FMA + F16C + BMI1/2", "Haswell..Coffee Lake / Zen 1-3"],
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SimdProfile::A76DotProd => &[
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"NEON + dotprod + fp16 + bf16+ + i8mm",
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"Pi 5 (BCM2712), Orange Pi 5 (RK3588), Apple M1+",
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],
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SimdProfile::A72Fast => &[
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"NEON 128-bit + crypto (AES/SHA-2/CRC32)",
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"Pi 4 (BCM2711), Pi 3-with-crypto, Orange Pi 4 — HWCAP cannot distinguish A72 from A53-with-crypto",
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],
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SimdProfile::A53Baseline => &[
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"NEON 128-bit baseline",
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"Rare in the wild — QEMU / minimal aarch64 without crypto",
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],
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SimdProfile::Scalar => &["No SIMD ISA recognised", "Fallback: scalar reference kernels"],
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};
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for line in summary {
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println!(" - {}", line);
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}
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}

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