feat(simd): I8/I16 SIMD vectors + slice-level int ops (#124, sprint A3)

Adds the signed-byte / signed-half SIMD parity surface for the burn↔ndarray
sprint:

Item 4 — types
  • simd_avx512.rs: native I8x64 (__m512i) + I16x32 (__m512i) via
    AVX-512BW intrinsics (add/sub/min/max/cmp_gt/saturating/abs/neg).
    Plus AVX2-native I8x32 / I16x16 (__m256i) so the 256-bit signed
    types live in the same module as F32x8 / F64x4.
  • simd_avx2.rs: scalar-array polyfills for I8x64 / I16x32 (the AVX2
    tier doesn't have a 64-byte signed type) and re-exports of the
    AVX2-native I8x32 / I16x16 from simd_avx512.rs for unified imports.
  • simd_neon.rs: NEON-native I8x16 (int8x16_t) + I16x8 (int16x8_t)
    via vaddq_s8 / vminq_s8 / vcgtq_s8 + paired/quadrupled scalar
    polyfills for I8x32 / I8x64 / I16x16 / I16x32.
  • simd.rs: scalar fallbacks for non-x86_64/aarch64 targets and
    re-exports for every active tier so consumers write
    use ndarray::simd::{I8x32, I8x64, I16x16, I16x32};

Item 5 — slice ops (new file simd_int_ops.rs)
  add_i8 / add_i16 / sub_i8 / sub_i16 (mutate-in-place, wrapping)
  dot_i8 -> i32  (overflow-safe accumulator)
  dot_i16 -> i64 (overflow-safe accumulator)
  min_i8 / max_i8 / min_i16 / max_i16
  Each chunks via the natural SIMD width of the active tier (64-byte
  AVX-512BW when available, 32-byte AVX2, 16-byte NEON) and finishes
  with a scalar tail.

Tests (+21 lib tests vs master baseline 1741 -> 1762):
  • simd_avx512::int_simd_tests: 9 tests (gated on target_feature=avx512f)
    pair-sum 64, signed boundaries, cmp_gt mask, saturating arithmetic.
  • simd_int_ops::tests: 11 tests
    misaligned tail lengths (63/65/127/129), 127i8 dot 127i8 x 64
    overflow safety, signed boundary min/max, empty-slice identity.
  • simd_avx2 polyfill build verified with
    RUSTFLAGS="-C target-feature=-avx512f".

Build host (this commit): AVX2 path (no avx512f at compile time -> uses
the polyfill in simd_avx2.rs and simd.rs scalar mod for I8x64/I16x32).

Co-authored-by: Claude <noreply@anthropic.com>

Author: AdaWorldAPI

src/lib.rs

@@ -252,6 +252,11 @@ pub mod simd_neon;
 #[allow(clippy::all, missing_docs, dead_code, unused_variables, unused_imports)]
 pub mod simd_wasm;
 
+/// Slice-level integer SIMD ops (i8/i16) — `add_i8`, `dot_i8`, `min_i8`, …
+#[cfg(feature = "std")]
+#[allow(missing_docs)]
+pub mod simd_int_ops;
+
 /// Pluggable linear algebra backends (native SIMD, MKL, OpenBLAS).
 #[cfg(feature = "std")]
 pub mod backend;

src/simd.rs

@@ -190,12 +190,14 @@ pub const PREFERRED_I16_LANES: usize = 16;
 
 #[cfg(all(target_arch = "x86_64", target_feature = "avx512f"))]
 pub use crate::simd_avx512::{
-    // 256-bit (AVX2 baseline, __m256/__m256d)
-    F32x8, F64x4, f32x8, f64x4,
+    // 256-bit (AVX2 baseline, __m256/__m256d/__m256i)
+    F32x8, F64x4, I8x32, I16x16, f32x8, f64x4, i8x32, i16x16,
     // 512-bit (native AVX-512, __m512/__m512d/__m512i)
     F32x16, F64x8, U8x64, I32x16, I64x8, U16x32, U32x16, U64x8,
+    I8x64, I16x32,
     F32Mask16, F64Mask8,
     f32x16, f64x8, u8x64, i32x16, i64x8, u32x16, u64x8,
+    i8x64, i16x32,
 };
 
 // BF16 types + batch conversion (always available — scalar fallback built in)
@@ -223,13 +225,15 @@ pub use crate::simd_avx512::{
 pub use crate::simd_avx512::{BF16x16, BF16x8};
 
 #[cfg(all(target_arch = "x86_64", not(target_feature = "avx512f")))]
-pub use crate::simd_avx512::{F32x8, F64x4, f32x8, f64x4};
+pub use crate::simd_avx512::{F32x8, F64x4, I8x32, I16x16, f32x8, f64x4, i8x32, i16x16};
 
 #[cfg(all(target_arch = "x86_64", not(target_feature = "avx512f")))]
 pub use crate::simd_avx2::{
     F32x16, F64x8, U8x64, I32x16, I64x8, U16x32, U32x16, U64x8,
+    I8x64, I16x32,
     F32Mask16, F64Mask8,
     f32x16, f64x8, u8x64, i32x16, i64x8, u32x16, u64x8,
+    i8x64, i16x32,
 };
 
 // ============================================================================
@@ -630,6 +634,62 @@ pub(crate) mod scalar {
     impl_int_type!(U32x16, u32, 16, 0u32);
     impl_int_type!(U64x8, u64, 8, 0u64);
 
+    // I8/I16 SIMD types (scalar fallback)
+    impl_int_type!(I8x64, i8, 64, 0i8);
+    impl_int_type!(I8x32, i8, 32, 0i8);
+    impl_int_type!(I16x32, i16, 32, 0i16);
+    impl_int_type!(I16x16, i16, 16, 0i16);
+
+    // I8x64 / I8x32 / I16x32 / I16x16 — AVX-512BW-style methods (scalar shape)
+    impl I8x64 {
+        #[inline(always)] pub fn zero() -> Self { Self([0i8; 64]) }
+        #[inline(always)] pub fn add(self, other: Self) -> Self { let mut o = [0i8; 64]; for i in 0..64 { o[i] = self.0[i].wrapping_add(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn sub(self, other: Self) -> Self { let mut o = [0i8; 64]; for i in 0..64 { o[i] = self.0[i].wrapping_sub(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn min(self, other: Self) -> Self { let mut o = [0i8; 64]; for i in 0..64 { o[i] = self.0[i].min(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn max(self, other: Self) -> Self { let mut o = [0i8; 64]; for i in 0..64 { o[i] = self.0[i].max(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn cmp_gt(self, other: Self) -> u64 {
+            let mut m: u64 = 0;
+            for i in 0..64 { if self.0[i] > other.0[i] { m |= 1u64 << i; } }
+            m
+        }
+    }
+    impl I8x32 {
+        #[inline(always)] pub fn zero() -> Self { Self([0i8; 32]) }
+        #[inline(always)] pub fn add(self, other: Self) -> Self { let mut o = [0i8; 32]; for i in 0..32 { o[i] = self.0[i].wrapping_add(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn sub(self, other: Self) -> Self { let mut o = [0i8; 32]; for i in 0..32 { o[i] = self.0[i].wrapping_sub(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn min(self, other: Self) -> Self { let mut o = [0i8; 32]; for i in 0..32 { o[i] = self.0[i].min(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn max(self, other: Self) -> Self { let mut o = [0i8; 32]; for i in 0..32 { o[i] = self.0[i].max(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn cmp_gt(self, other: Self) -> u32 {
+            let mut m: u32 = 0;
+            for i in 0..32 { if self.0[i] > other.0[i] { m |= 1u32 << i; } }
+            m
+        }
+    }
+    impl I16x32 {
+        #[inline(always)] pub fn zero() -> Self { Self([0i16; 32]) }
+        #[inline(always)] pub fn add(self, other: Self) -> Self { let mut o = [0i16; 32]; for i in 0..32 { o[i] = self.0[i].wrapping_add(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn sub(self, other: Self) -> Self { let mut o = [0i16; 32]; for i in 0..32 { o[i] = self.0[i].wrapping_sub(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn min(self, other: Self) -> Self { let mut o = [0i16; 32]; for i in 0..32 { o[i] = self.0[i].min(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn max(self, other: Self) -> Self { let mut o = [0i16; 32]; for i in 0..32 { o[i] = self.0[i].max(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn cmp_gt(self, other: Self) -> u32 {
+            let mut m: u32 = 0;
+            for i in 0..32 { if self.0[i] > other.0[i] { m |= 1u32 << i; } }
+            m
+        }
+    }
+    impl I16x16 {
+        #[inline(always)] pub fn zero() -> Self { Self([0i16; 16]) }
+        #[inline(always)] pub fn add(self, other: Self) -> Self { let mut o = [0i16; 16]; for i in 0..16 { o[i] = self.0[i].wrapping_add(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn sub(self, other: Self) -> Self { let mut o = [0i16; 16]; for i in 0..16 { o[i] = self.0[i].wrapping_sub(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn min(self, other: Self) -> Self { let mut o = [0i16; 16]; for i in 0..16 { o[i] = self.0[i].min(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn max(self, other: Self) -> Self { let mut o = [0i16; 16]; for i in 0..16 { o[i] = self.0[i].max(other.0[i]); } Self(o) }
+        #[inline(always)] pub fn cmp_gt(self, other: Self) -> u16 {
+            let mut m: u16 = 0;
+            for i in 0..16 { if self.0[i] > other.0[i] { m |= 1u16 << i; } }
+            m
+        }
+    }
+
     // Extra methods for U16x32 (widen/narrow, shift, multiply)
     impl U16x32 {
         #[inline(always)]
@@ -1012,6 +1072,10 @@ pub(crate) mod scalar {
     #[allow(non_camel_case_types)] pub type u64x8 = U64x8;
     #[allow(non_camel_case_types)] pub type f32x8 = F32x8;
     #[allow(non_camel_case_types)] pub type f64x4 = F64x4;
+    #[allow(non_camel_case_types)] pub type i8x64 = I8x64;
+    #[allow(non_camel_case_types)] pub type i8x32 = I8x32;
+    #[allow(non_camel_case_types)] pub type i16x32 = I16x32;
+    #[allow(non_camel_case_types)] pub type i16x16 = I16x16;
 }
 
 // aarch64: F32x16/F64x8 come from the real NEON paired-load implementation
@@ -1036,9 +1100,11 @@ pub use scalar::{
 pub use scalar::{
     F32x16, F64x8, U8x64, I32x16, I64x8, U16x32, U32x16, U64x8,
     F32x8, F64x4,
+    I8x64, I8x32, I16x32, I16x16,
     F32Mask16, F64Mask8,
     f32x16, f64x8, u8x64, i32x16, i64x8, u32x16, u64x8,
     f32x8, f64x4,
+    i8x64, i8x32, i16x32, i16x16,
 };
 
 // Scalar BF16 conversion — always available on all platforms

src/simd_avx2.rs

@@ -8,6 +8,10 @@
 
 use crate::simd_avx512::{f32x8, f64x4};
 
+// AVX2-native I8x32 / I16x16 live in simd_avx512.rs (256-bit __m256i types).
+// Re-export so consumers see a unified `crate::simd_avx2::I8x32` symbol.
+pub use crate::simd_avx512::{I8x32, I16x16, i8x32, i16x16};
+
 // ============================================================================
 // AVX2 lane counts (half of AVX-512)
 // ============================================================================
@@ -772,6 +776,47 @@ macro_rules! avx2_int_type {
 }
 
 avx2_int_type!(U8x64, u8, 64, 0u8);
+avx2_int_type!(I8x64, i8, 64, 0i8);
+avx2_int_type!(I16x32, i16, 32, 0i16);
+
+// I8x64 / I16x32: AVX2 scalar polyfill — methods matching the AVX-512BW API
+impl I8x64 {
+    #[inline(always)]
+    pub fn zero() -> Self { Self([0i8; 64]) }
+    #[inline(always)]
+    pub fn add(self, other: Self) -> Self { let mut o = [0i8; 64]; for i in 0..64 { o[i] = self.0[i].wrapping_add(other.0[i]); } Self(o) }
+    #[inline(always)]
+    pub fn sub(self, other: Self) -> Self { let mut o = [0i8; 64]; for i in 0..64 { o[i] = self.0[i].wrapping_sub(other.0[i]); } Self(o) }
+    #[inline(always)]
+    pub fn min(self, other: Self) -> Self { let mut o = [0i8; 64]; for i in 0..64 { o[i] = self.0[i].min(other.0[i]); } Self(o) }
+    #[inline(always)]
+    pub fn max(self, other: Self) -> Self { let mut o = [0i8; 64]; for i in 0..64 { o[i] = self.0[i].max(other.0[i]); } Self(o) }
+    #[inline(always)]
+    pub fn cmp_gt(self, other: Self) -> u64 {
+        let mut m: u64 = 0;
+        for i in 0..64 { if self.0[i] > other.0[i] { m |= 1u64 << i; } }
+        m
+    }
+}
+
+impl I16x32 {
+    #[inline(always)]
+    pub fn zero() -> Self { Self([0i16; 32]) }
+    #[inline(always)]
+    pub fn add(self, other: Self) -> Self { let mut o = [0i16; 32]; for i in 0..32 { o[i] = self.0[i].wrapping_add(other.0[i]); } Self(o) }
+    #[inline(always)]
+    pub fn sub(self, other: Self) -> Self { let mut o = [0i16; 32]; for i in 0..32 { o[i] = self.0[i].wrapping_sub(other.0[i]); } Self(o) }
+    #[inline(always)]
+    pub fn min(self, other: Self) -> Self { let mut o = [0i16; 32]; for i in 0..32 { o[i] = self.0[i].min(other.0[i]); } Self(o) }
+    #[inline(always)]
+    pub fn max(self, other: Self) -> Self { let mut o = [0i16; 32]; for i in 0..32 { o[i] = self.0[i].max(other.0[i]); } Self(o) }
+    #[inline(always)]
+    pub fn cmp_gt(self, other: Self) -> u32 {
+        let mut m: u32 = 0;
+        for i in 0..32 { if self.0[i] > other.0[i] { m |= 1u32 << i; } }
+        m
+    }
+}
 
 // ── U8x64 byte-level operations (scalar fallback for AVX2 tier) ──────────
 // These match the AVX-512 U8x64 methods in simd_avx512.rs.
@@ -1007,6 +1052,10 @@ pub type i64x8 = I64x8;
 pub type u32x16 = U32x16;
 #[allow(non_camel_case_types)]
 pub type u64x8 = U64x8;
+#[allow(non_camel_case_types)]
+pub type i8x64 = I8x64;
+#[allow(non_camel_case_types)]
+pub type i16x32 = I16x32;
 
 #[cfg(test)]
 mod tests {