docs(hhtl): GridLake pre-sprint prompt (PR-X1 + PR-X2) — column-substrate identity made concrete

Folds the gaussian-splat session's feedback into a copy-paste-ready
pre-sprint kickoff for PR-X1 (MultiLaneColumn carrier) + PR-X2 (#[derive(SoA)]
proc-macro). Grounded verbatim in PR #162's column-substrate identity so
nothing floats — every claim cites a line range in a doc that just merged
to master.

## Quoted verbatim from PR #162 (master commit c8f4af6)

1. **Column-substrate identity** (consolidation doc lines 126-220) — the
   load-bearing architectural reason MultiLaneColumn exists. The full Lance
   / Arrow / ndarray-SoA diagram + the three load-bearing passages
   ("one physical representation, end to end", "ndarray amortises the SIMD
   primitive across the whole stack", "the column IS the SoA IS the ndarray
   buffer") are reproduced inline in § "Why this exists".

2. **Sprint sequencing** (execution prompt lines 76-91) — the 8-week
   schedule GridLake patches. Q-NEW-1 marker calls out the two viable
   insertion points (path a: W2.5 prerequisite slot; path b: X10-A13/A14
   absorption) with trade-offs and a recommendation, leaves the decision
   to the plan-review savant at preflight.

3. **W1 PR-X10 kickoff format** (execution prompt lines 91-144) — mirrored
   exactly in the final § "Sprint kickoff — W2.5 (path a) or W1-W2 inline
   (path b)" block. READ FIRST + WORKER DECOMPOSITION + PROTOCOL A +
   ACCEPTANCE GATES + PR FORMAT + BUDGET + NEXT SPRINTS all present.

4. **Canary gates** (canary plan lines 64-127) — inherited as GridLake's
   done criteria, with each canary gate mapped to a specific GridLake
   primitive contribution (e.g., A2's pad_to_lanes invariant gates
   Correctness.1 bit-exact; A3's bench_no_alloc gates Performance.6
   working set ≤ 1 MB; sentinel-qa unsafe audit gates Inhabitance.3 zero
   P0 SAFETY).

## Negative constraints

§ "Forbidden" carries the verbatim heel_f64x8 absorption note from
pr-x10-linalg-core-design.md, with the directive: if a GridLake
SIMD-staged inner loop wants a distance kernel, it calls
crate::hpc::linalg::distance::l2_f64_simd (lands in W2 as PR-X10 A6),
not a duplicate in crate::simd_soa::*. Plus four more negative
constraints: no new SIMD types, no Lance file I/O, no cross-column
compute, no runtime schema registry.

## Worker decomposition (4 max-fan-out)

- A1 (sequential) — MultiLaneColumn carrier with 7 lane iterators
  (u8x64 / u16x32 / u32x16 / u64x8 / f32x16 / f64x8 / bf16x32)
- A2 (parallel) — simd-soa-derive proc-macro crate (#[derive(SoA)] +
  #[soa(pad_to_lanes=N)] with strict invariant that pad_to_lanes does
  NOT change len() semantics)
- A3 (parallel) — bench harness (bench_no_alloc + throughput vs raw
  chunks_exact + lane-width swap cache friendliness + Arc clone O(1))
- A4 (parallel) — integration probes (splat3d backward-compat +
  nars 10k-seed scalar-vs-SoA parity + Arrow round-trip zero-copy)

## Why this is its own pre-sprint and not part of PR-X10

The Q-NEW-1 framing is honest: path (b) absorbs GridLake into PR-X10 as
A13/A14 and saves 0.5 weeks, but the doc recommends path (a) because
column-substrate identity is a different concern from linalg primitives
under the same coordinator. The plan-review savant decides at preflight;
both paths are documented end-to-end so either choice can spawn
immediately.

## Status

- File lives at .claude/knowledge/hhtl-gridlake-pre-sprint-prompt.md
- Fresh branch claude/gridlake-pre-sprint-prompt off post-#162 master
- No PR opened — awaiting user instruction

Author: claude