fix(simd): SimdProfile::detect() consults amx_available() — Risk #3 closure

Integration plan risk #3 ("Detection robustness across hypervisors"):
CPUID may advertise AMX-TILE while the OS/hypervisor has not enabled
the tile XSAVE state. Without the OS-level check, the dispatch table
routes to AMX kernels that SIGILL at first use.

Fix: SimdProfile::detect() now reads `simd_amx::amx_available()` (the
existing 4-step gate: CPUID → OSXSAVE → XCR0[17,18] → arch_prctl
XCOMP_PERM on Linux 5.19+) and demotes when CPUID and OS disagree.
The GraniteRapids and SapphireRapids arms now require both the CPUID
bits AND `amx_usable`; the Zen4Avx512 arm catches SPR-class CPUID
with locked-down hypervisor XSAVE so dispatch falls to the AVX-512
BF16/FP16 path instead.

Verified on the build host (Sapphire Rapids silicon, kernel 6.18.5):
  - CPUID reports amx_tile=1, amx_int8=1, amx_bf16=1 (all true)
  - simd_amx::amx_available() returns false (hypervisor masks
    XCR0[17,18] or the arch_prctl(XCOMP_PERM) request fails)
  - SimdProfile::detect() correctly resolves to Zen4Avx512, not
    SapphireRapids — the AMX kernels are not reachable from
    dispatch on this OS state.

Without this fix, the e40f3a3 detect path would have resolved to
SapphireRapids on this exact silicon/OS combination, then SIGILL'd
the first time a dispatch table called an AMX kernel. Bug closed
before any consumer was wired to the dispatch table.

The probe binary (examples/simd_profile_probe.rs) gains a new "AMX
gating (CPUID vs OS)" section so the CPUID-vs-OS gap is visible
without reading source. Format mirrors how the matrix-doc cell
summary appears: terse, two lines plus an optional demotion note
when the bits disagree.

Pinned mode (cpu-* cargo features) intentionally bypasses this gate
since pinning is a build-time assertion that the target OS supports
the chosen variant — pinned binaries are non-portable by design.

Tests: 2077/2077 lib pass. cargo clippy --lib clean under default
and --features cpu-spr. Behaviour on hardware with proper AMX
enablement (full prctl path success) is unchanged: SapphireRapids
still resolves to SapphireRapids when amx_available() returns true.

Author: claude

examples/simd_profile_probe.rs

@@ -49,6 +49,27 @@ fn main() {
     print_caps(&caps);
     println!();
 
+    // ── AMX OS-state probe (Risk #3 from integration plan) ────────
+    // SimdCaps reports raw CPUID. SimdProfile::detect() additionally
+    // consults `simd_amx::amx_available()` which gates on
+    // OSXSAVE + XCR0[17,18] + arch_prctl(XCOMP_PERM). If CPUID says
+    // AMX-TILE but the OS/hypervisor doesn't enable the XSAVE state,
+    // dispatch demotes from SPR/GNR to Zen4Avx512 (AVX-512 BF16 path
+    // instead of AMX tiles). Surfacing the gap here lets a reviewer
+    // see when CPUID-vs-OS disagree without reading source.
+    #[cfg(target_arch = "x86_64")]
+    {
+        let cpuid_says_amx = caps.amx_tile && caps.amx_int8;
+        let os_allows_amx = ndarray::simd_amx::amx_available();
+        println!("AMX gating (CPUID vs OS):");
+        println!("  CPUID amx_tile+amx_int8: {}", cpuid_says_amx);
+        println!("  OS XSAVE/prctl gate:     {}", os_allows_amx);
+        if cpuid_says_amx && !os_allows_amx {
+            println!("  → CPUID-reported AMX is OS-DEMOTED — dispatch falls back to AVX-512 path");
+        }
+        println!();
+    }
+
     // ── ARM-specific sub-profile (heuristic; deployment-pragmatic) ──
     let arm = caps.arm_profile();
     if !matches!(arm, ArmProfile::NotArm) {

src/hpc/simd_profile.rs

@@ -86,22 +86,34 @@ impl SimdProfile {
         #[cfg(target_arch = "x86_64")]
         {
             let caps = simd_caps();
+            // Risk #3 from the integration plan ("Detection robustness
+            // across hypervisors"): CPUID may report AMX-TILE while the
+            // OS has not enabled the tile XSAVE state. In that case AMX
+            // instructions SIGILL despite the CPUID bit being set.
+            // `simd_amx::amx_available()` runs the full 4-step gate
+            // (CPUID + OSXSAVE + XCR0 bits 17/18 + arch_prctl
+            // XCOMP_PERM). Demote to the no-AMX dispatch branch when
+            // the OS check fails — typically resolves as Zen4Avx512 on
+            // SPR-class CPUID with locked-down hypervisor XSAVE state.
+            let amx_usable = caps.amx_tile && crate::simd_amx::amx_available();
             // GraniteRapids: AMX-FP16 (CPUID 7,1 EAX bit 21). Must be
             // checked first because GNR is a strict superset of SPR.
-            if caps.has_amx_fp16() {
+            if amx_usable && caps.amx_fp16 {
                 return SimdProfile::GraniteRapids;
             }
             // SapphireRapids / EmeraldRapids: AMX-TILE + AMX-BF16 +
             // AVX-512-FP16. EmeraldRapids has identical ISA — same variant.
-            if caps.amx_tile && caps.amx_bf16 && caps.avx512fp16 {
+            if amx_usable && caps.amx_bf16 && caps.avx512fp16 {
                 return SimdProfile::SapphireRapids;
             }
-            // Zen4 / Zen5: AVX-512 + VBMI + BF16 + FP16, but no AMX.
+            // Zen4 / Zen5: AVX-512 + VBMI + BF16 + FP16, but no usable
+            // AMX. The `!amx_usable` guard also catches OS-demoted SPR
+            // silicon so it resolves here instead of as SapphireRapids.
             if caps.avx512f
                 && caps.avx512vbmi
                 && caps.avx512bf16
                 && caps.avx512fp16
-                && !caps.amx_tile
+                && !amx_usable
             {
                 return SimdProfile::Zen4Avx512;
             }