@@ -2038,10 +2038,18 @@ llm_graph_result * llama_context::process_ubatch(const llama_ubatch & ubatch, ll
20382038 phase2_gf = model.build_graph (gparams, nullptr , nullptr , &moe_weight_cache);
20392039 if (!phase2_gf) { ret = GGML_STATUS_FAILED ; return nullptr ; }
20402040 ggml_backend_sched_reset (sched.get ());
2041- for (int i = 0 ; i < ggml_graph_n_nodes (phase2_gf); i++)
2042- ggml_backend_sched_set_tensor_backend (sched.get (), ggml_graph_node (phase2_gf, i), gpu);
2043- for (int i = 0 ; i < ggml_graph_n_leafs (phase2_gf); i++)
2044- ggml_backend_sched_set_tensor_backend (sched.get (), ggml_graph_leaf (phase2_gf, i), gpu);
2041+ for (int i = 0 ; i < ggml_graph_n_nodes (phase2_gf); i++) {
2042+ ggml_tensor * t = ggml_graph_node (phase2_gf, i);
2043+ auto [tid, il] = h2_hijack.match_name (t->name );
2044+ if (tid >= 0 )
2045+ ggml_backend_sched_set_tensor_backend (sched.get (), t, gpu);
2046+ }
2047+ for (int i = 0 ; i < ggml_graph_n_leafs (phase2_gf); i++) {
2048+ ggml_tensor * t = ggml_graph_leaf (phase2_gf, i);
2049+ auto [tid, il] = h2_hijack.match_name (t->name );
2050+ if (tid >= 0 )
2051+ ggml_backend_sched_set_tensor_backend (sched.get (), t, gpu);
2052+ }
20452053 force_idxs_to_cpu ();
20462054 if (!ggml_backend_sched_alloc_graph (sched.get (), phase2_gf)) { ret = GGML_STATUS_ALLOC_FAILED ; return nullptr ; }
20472055
@@ -2090,24 +2098,24 @@ llm_graph_result * llama_context::process_ubatch(const llama_ubatch & ubatch, ll
20902098
20912099 if (do_cuda && !h2_hijack.captured ) {
20922100 // --- CAPTURE PATH ---
2093- // 1. Reset + force All Phase 2 ops/srcs to GPU, then alloc
2101+ // 1. Reset + force matched MoE tensors to GPU
20942102 ggml_backend_sched_reset (sched.get ());
2095- for (int i = 0 ; i < ggml_graph_n_nodes (phase2_gf); i++)
2096- ggml_backend_sched_set_tensor_backend (sched.get (), ggml_graph_node (phase2_gf, i), gpu);
2103+ for (int i = 0 ; i < ggml_graph_n_nodes (phase2_gf); i++) {
2104+ ggml_tensor * t = ggml_graph_node (phase2_gf, i);
2105+ auto [tid, il] = h2_hijack.match_name (t->name );
2106+ if (tid >= 0 )
2107+ ggml_backend_sched_set_tensor_backend (sched.get (), t, gpu);
2108+ }
2109+ for (int i = 0 ; i < ggml_graph_n_leafs (phase2_gf); i++) {
2110+ ggml_tensor * t = ggml_graph_leaf (phase2_gf, i);
2111+ auto [tid, il] = h2_hijack.match_name (t->name );
2112+ if (tid >= 0 )
2113+ ggml_backend_sched_set_tensor_backend (sched.get (), t, gpu);
2114+ }
20972115 force_idxs_to_cpu ();
20982116 if (!ggml_backend_sched_alloc_graph (sched.get (), phase2_gf)) {
20992117 ret = GGML_STATUS_ALLOC_FAILED ; return nullptr ;
21002118 }
2101- #ifdef GGML_USE_CUDA
2102- fprintf (stderr, " phase2_dump: %d nodes, %d leafs\n " ,
2103- ggml_graph_n_nodes (phase2_gf), ggml_graph_n_leafs (phase2_gf));
2104- for (int i = 0 ; i < ggml_graph_n_nodes (phase2_gf); i++) {
2105- ggml_tensor * t = ggml_graph_node (phase2_gf, i);
2106- ggml_backend_t be_t = ggml_backend_sched_get_tensor_backend (sched.get (), t);
2107- fprintf (stderr, " phase2[node %d]: %s op=%d cuda=%d\n " , i, t->name , (int )t->op ,
2108- be_t ? ggml_backend_is_cuda (be_t ) : -1 );
2109- }
2110- #endif
21112119 if (res->t_logits ) ggml_backend_sched_set_tensor_backend (sched.get (), res->t_logits , be);
21122120 if (res->t_embd ) ggml_backend_sched_set_tensor_backend (sched.get (), res->t_embd , be);
21132121
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