Fix typos, formatting for contrib readmes (#437)

Author: chrisib

software/contrib/bernoulli_gates.md

@@ -1,43 +1,53 @@
 # Bernoulli Gates
 
-author: Bridgee
+This script is based on Mutable Instruments Branches. Because EuroPi only haa a pair of digital/analogue
+inputs, the dual Bernoulli gates share the same clock (from the digital input), and only one Bernoulli
+gate has CV input.
 
-date: 03/13/22
+A Bernoulli gate takes a logic signal (trigger or gate) as an input, and routes it to either of its
+two outputs according to a random coin toss.
 
-labels: Random
+## Inputs & Outputs
 
-### General
-This app is based on Mutable Instruments Branches. Because EuroPi only have a pair of digital/analogue inputs, the dual Bernoulli gates share the same clock (from the digital input), and only one Bernoulli gate have CV input.
+Inputs:
+- `din`: trigger/clock
+- `ain`: probability control of gate 1 (summed with Knob 1)
+- `k1`: probability control of gate 1
+- `k2`: probability control of gate 2
+- `b1`: mode switch of gate 1
+- `b2`: mode switch of gate 2
 
-A Bernoulli gate takes a logic signal (trigger or gate) as an input, and routes it to either of its two outputs according to a random coin toss.
+Outputs:
+- `cv1`: output A of gate 1
+- `cv2`: output B of gate 1
+- `cv3`: copy of input trigger/clock
+- `cv4`: output A of gate 2
+- `cv5`: output B of gate 2
+- `cv6`: logical AND of both output A (`cv1` and `cv4`)
 
-Knob 1 adjusts the probability of the Bernoulli gate 1, and Knob 2 adjusts the probability of the Bernoulli gate 2.
+Turning a knob anticlockwise increases the probability that a signal will be routed to the
+corresponding gate's A-output, while turning it clockwise increases the probablility of the signal
+being routed to the gate's B-output. At 12-o'clock the probability of either is 50/50. Fully
+anticlockwise the probability of either is 100/0 and fully clockwise is 0/100.
 
-Button 1 switches the mode of gate 1 between trigger mode, toggle mode, and gate mode (latch mode), and Button 2 switches the mode of gate 2 between trigger mode, toggle mode, and gate mode (latch mode).
+Gate modes can be switched between
+- trigger: `Tr`
+- toggle: `Tg`
+- gate (latch): `G`
+by pressing the buttons. These modes are described in more detail below.
 
-### Tigger mode (Tr)
+## Tigger mode (Tr)
 
-When the **trigger mode** is enabled, an output A/B changes to +5V for 10ms every time they are activated by the corresponding Bernoulli gate.
+When the **trigger mode** is enabled, an output A/B changes to +5V for 10ms every time they are
+activated by the corresponding Bernoulli gate.
 
-### Gate mode/Latch mode (G)
-
-When the **gate mode** is enabled, an output A/B stays at +5V until the other output gets activated.
-
-### Toggle mode (Tg)
-
-In **toggle mode**, the module associates the “heads” and “tails” outcomes to a different pair of decisions: “continue sending the trigger to the same output as before” and “send the trigger to the opposite output”. As a result, when the probability knob 1 is set to its maximum value, the trigger will alternate between outputs A and B.
+## Toggle mode (Tg)
 
+In **toggle mode**, the module associates the “heads” and “tails” outcomes to a different pair of
+decisions: “continue sending the trigger to the same output as before” and “send the trigger to the
+opposite output”. As a result, when the probability knob 1 is set to its maximum value, the trigger
+will alternate between outputs A and B.
 
+## Gate mode/Latch mode (G)
 
-
-
-    digital in: trigger/clock
-    analogue in: probability control of gate 1 (summed with Knob 1)
-    knob 1: probability control of gate 1
-    knob 2: probability control of gate 2
-    button 1: mode switch of gate 1
-    button 2: mode switch of gate 2
-    cv1/cv2: output A/B of gate 1
-    cv4/cv5: output A/B of gate 2
-    cv3: copy of trigger/clock
-    cv6: logic AND of the two output A
+When the **gate mode** is enabled, an output A/B stays at +5V until the other output gets activated.

software/contrib/bezier.md

@@ -5,41 +5,45 @@ This script generates two random CV outputs using [Bezier curves](https://en.wik
 This work is inspired by the [ADDAC507](https://www.addacsystem.com/en/products/modules/addac500-series/addac507),
 a collaboration between ADDAC System and [Monotrail](https://youtu.be/9PxVmeMrOoQ?si=GsNDKNipjHtBIPT1)
 
-## Input & Output
+## Inputs & Outputs
 
-The module has two separate output channels, referred to as A and B. Each has identical controls, though channel B's
-controls can only be accessed by holding `b2`.  Note that when changing channels, the knobs will "lock" in their
-previous positions, so you may need to sweep the knob to unlock it.
+The module has two separate output channels, referred to as A and B. Each has identical controls,
+though channel B's controls can only be accessed by holding `b2`.  Note that when changing channels,
+the knobs will "lock" in their previous positions, so you may need to sweep the knob to unlock it.
 
 - `b1` -- press to change the clipping mode for both channels (see below)
 - `b2` -- hold to change `k1` and `k2` to channel B input
 
 - `k1` -- set the frequency of channel A or B
 - `k2` -- set the curve of channel A or B
-- `ain` -- configurable CV input to control either the frequency or curve (see below for how to set routing)
-- `din` -- on a rising edge, force channels A and B to choose new goal voltages. This will not generate an output gate
-   on `cv4` (see below), but may change the gate state on `cv5` and `cv6`.
+- `ain` -- configurable CV input to control either the frequency or curve (see below for how to set
+  routing)
+- `din` -- on a rising edge, force channels A and B to choose new goal voltages. This will not
+  generate an output gate on `cv4` (see below), but may change the gate state on `cv5` and `cv6`.
 
 - `cv1` -- CV output from channel A
 - `cv2` -- CV output from channel B
 - `cv3` -- the average of channel A and B CV outputs
 - `cv4` -- gate output of channel A
 - `cv5` -- gate output of channel B
-- `cv6` -- logic combination of gate outputs of channels A and B (see below for how to configure the logic mode)
+- `cv6` -- logic combination of gate outputs of channels A and B (see below for how to configure the
+  logic mode)
 
 Gate outputs are different for channels A and B:
-- Channel A (`cv4`) outputs a 10ms trigger every time a new sample is generated (determined by the frequency)
-- Channel B (`cv5`) is high whenever its voltage output is higher than 50%. e.g. if the range is set to 0-10V, `cv5`
-  will be high if `cv2` is 5V or more.
-
-Patching a clock/gate/trigger signal into `din` will force the output channels to choose a new goal voltage. This can
-(and frequently will) cause an abrupt change in the CV output of channels A and B, rather than the smoothly changing
+- Channel A (`cv4`) outputs a 10ms trigger every time a new sample is generated (determined by the
+  frequency)
+- Channel B (`cv5`) is high whenever its voltage output is higher than 50%. e.g. if the range is set
+  to 0-10V, `cv5` will be high if `cv2` is 5V or more.
+
+Patching a clock/gate/trigger signal into `din` will force the output channels to choose a new goal
+voltage. This can (and frequently will) cause an abrupt change in the CV output of channels A and B,
+rather than the smoothly changing
 voltages they normally output.
 
 ## Additional Configuration
 
-The script has additional parameters that can be set by manually editing/creating `/config/Bezier.json`. The default
-values for this file are below:
+The script has additional parameters that can be set by manually editing/creating
+`/config/Bezier.json`. The default values for this file are below:
 
 ```json
 {
@@ -55,38 +59,44 @@ The following fields may be set:
 
 - `MIN_VOLTAGE` -- the minimum voltage that channel A or channel B may output. Default: 0.0
 - `MAX_VOLTAGE` -- the maximum voltage that channel A or channel B may output. Default 10.0
-- `AIN_MODE` -- changes what parameter voltage to `ain` controls. Must be one of `curve` or `frequency`. Default: `frequency`
-- `LOGIC_MODE` -- sets the logical operation used to determine the gate output of `cv6`. Must be one of
-   `and`, `or`, `xor`, `nand`, `nor`, or `xnor`. Default: `xor`.
-- `MIN_FREQUENCY` -- the minumum frequency (Hz) for choosing new random values. Must be between 0.001 and 10.0. Default: 0.01
-- `MAX_FREQUENCY` -- the maximum frequency (Hz) for choosing new random values. Must be between 0.001 and 10.0. Default: 1.0
+- `AIN_MODE` -- changes what parameter voltage to `ain` controls. Must be one of `curve` or
+  `frequency`. Default: `frequency`
+- `LOGIC_MODE` -- sets the logical operation used to determine the gate output of `cv6`. Must be one
+  of `and`, `or`, `xor`, `nand`, `nor`, or `xnor`. Default: `xor`.
+- `MIN_FREQUENCY` -- the minumum frequency (Hz) for choosing new random values. Must be between
+  0.001 and 10.0. Default: 0.01
+- `MAX_FREQUENCY` -- the maximum frequency (Hz) for choosing new random values. Must be between
+  0.001 and 10.0. Default: 1.0
 - `MAX_INPUT_VOLTAGE` -- the maximum CV input voltage (default: 10.0)
 
 Note that the maximum and minimum voltages must be defined such that:
 - `MIN_VOLTAGE` is less than `MAX_VOLTAGE`
 - `MIN_VOLTAGE` and `MAX_VOLTAGE` are positive
-- `MIN_VOLTAGE` and `MAX_VOLTAGE` do not fall outside the range defined by the module's master configuration
+- `MIN_VOLTAGE` and `MAX_VOLTAGE` do not fall outside the range defined by the module's master
+  configuration
 - `MAX_INPUT_VOLTAGE` is less than the module's master configuration.
 
-See [Configuration](/software/CONFIGURATION.md) for more information on input & output voltage options for the
-entire module.
+See [Configuration](/software/CONFIGURATION.md) for more information on input & output voltage
+options for the entire module.
 
-If you plan on using CV to control Bezier, make sure you set the maximum input voltage according to your modules'
-output.  For example if you plan on connecting it to an LFO that outputs 0-5V, you may find it helpful to set the
-`MAX_INPUT_VOLTAGE` to `5.0` to allow the full modulation range.  If your LFO is bipolar (e.g. `+/-5V`), the input
-will be clamped at 0 as EuroPi does not support bipolar CV input.  In this case, the use of a voltage rectifier is
-recommended.
+If you plan on using CV to control Bezier, make sure you set the maximum input voltage according to
+your modules' output.  For example if you plan on connecting it to an LFO that outputs 0-5V, you may
+find it helpful to set the `MAX_INPUT_VOLTAGE` to `5.0` to allow the full modulation range.  If your
+LFO is bipolar (e.g. `+/-5V`), the input will be clamped at 0 as EuroPi does not support bipolar CV
+input.  In this case, the use of a voltage rectifier is recommended.
 
 ## Clipping mode
 
-The output can behave in one of 3 ways if the output wave moves outside the defined maximum/minimum voltage range:
+The output can behave in one of 3 ways if the output wave moves outside the defined maximum/minimum
+voltage range:
 - `limit` -- the output is clipped to the maximum/minimum value
 - `fold` -- the output is flipped such that the shape of the curve is reflected
 - `thru` -- the output wraps around through the opposite end of the range
 
 ## Curve Shapes
 
-The shape of the bezier curves is defined by the "curve constant" `k`. This value lies in the range `[-1, 1]`, and is
+The shape of the bezier curves is defined by the "curve constant" `k`. This value lies in the range
+`[-1, 1]`, and is
 interpreted as follows:
 - `0.0` -- linear interpolation between voltages
 - `k < 0` -- horizontal approach to each new voltage
@@ -95,16 +105,17 @@ interpreted as follows:
 The following image illustrates this concept, copied from the ADDAC507 manual:
 ![Bezier Curves](bezier-docs/curve-knob.png.png)
 
-Negative values of `k` will generally result in a smoother overall shape to the output voltage. Positive values will
-have more abrupt changes in voltage whenever a new goal value is generated.
+Negative values of `k` will generally result in a smoother overall shape to the output voltage.
+Positive values will have more abrupt changes in voltage whenever a new goal value is generated.
 
 ## CV Control
 
-If CV control is set to `frequency` (the default), `ain` will accept positive voltage, increasing the frequency of both
-channels as voltage increases.
+If CV control is set to `frequency` (the default), `ain` will accept positive voltage, increasing
+the frequency of both channels as voltage increases.
 
-If CV control is set to `curve`, `ain` will accept positive voltage, changing the curve constant of both channels. The
-channels' curve constants are set to the average between the knob value (`[-1, 1]`) and the CV value:
+If CV control is set to `curve`, `ain` will accept positive voltage, changing the curve constant of
+both channels. The channels' curve constants are set to the average between the knob value
+(`[-1, 1]`) and the CV value:
 - `0V` is equivalent to a curve constant of `-1`
 - `50%` of `MAX_INPUT_VOLTAGE` is equivalent to a curve constant of `0`
 - `100%` of `MAX_INPUT_VOLTAGE` is equivalent to a curve constant of `+1`

software/contrib/bit_garden.md

@@ -1,14 +1,8 @@
 # Bit Garden - pseudo-random deterministic repeated triggers
 
-author: Adam Wonak (github.com/awonak)
-
-date: 2024-03-21
-
-labels: triggers, random
-
 Connect a trigger or gate source to the Digital input and the each output will
 mirror that signal according to a decreasing deterministic probability pattern
-set by the seed value. Use the Analog input as a trigger to get a new random 
+set by the seed value. Use the Analog input as a trigger to get a new random
 seed. From the main page, use the left knob adjust the pattern length. The
 right knob will scroll through each output to show the current trigger pattern
 for that output. Left button will change the cv output mode from Trigger

software/contrib/bouncing_pixels.md

@@ -1,11 +1,5 @@
 # Bouncing Pixels
 
-author: [Jorin](https://github.com/jorins)
-
-date: 2025-04-12
-
-labels: gates, random, simulation, triggers
-
 Pixels bounce around the display and trigger gates when hitting the edges.
 Inspired by the classic bouncing DVD logo!
 
@@ -41,7 +35,7 @@ One possible over and under speed behaviour is that pixels are deactivated.
 When deactivated, a pixel will not be processed or rendered until reset. Resets
 can be manually triggered by pressing B1 or using the digital input (must be
 configured). A reset is automatically triggered when all pixels in play are
-deactivated. 
+deactivated.
 
 ## Outputs
 
@@ -167,7 +161,7 @@ controller.
 ## Known issues & limitations
 
 * Gate lengths are not entirely precise. They're guaranteed to be at least the
-  set length, but they may exceed it slightly on account of running on 
+  set length, but they may exceed it slightly on account of running on
   tick-based timers.
 * Corners aren't actually corners, they're just the top and bottom most
   parts of the side edges. This means that if a pixel is traveling parallel and
@@ -198,4 +192,4 @@ you can do:
   under speed behaviour.
 * Allow more in-app configuration instead of relying on the configuration file.
 * Implement visual feedback on the locked knob inputs. This would make the use
-  of the second layer knobs easier.
+  of the second layer knobs easier.

software/contrib/clock_mod.md

@@ -2,8 +2,9 @@
 
 This program performs clock multiplications and divisions based on an incoming gate signal on DIN.
 
-Each output is a multiple or a division of the incoming clock signal on `DIN`.  The duration of the output gates
-are not adjustable and are fixed to approximately a 50% duty cycle (some rounding will occur).
+Each output is a multiple or a division of the incoming clock signal on `DIN`.  The duration of the
+output gates are not adjustable and are fixed to approximately a 50% duty cycle (some rounding will
+occur).
 
 ## I/O Mapping
 
@@ -17,24 +18,25 @@ are not adjustable and are fixed to approximately a 50% duty cycle (some roundin
 | `k2`          | Clock modifier for CV4/5/6                                        |
 | `cv1-6`       | Multiplied/divided clock signals                                  |
 
-The outputs will begin firing automatically when clock signals are received on `din`, and will stop if the input
-signals are stopped for 5s or longer.  Upon stopping all output channels will reset.  (NOTE: this means the signal
-coming into `din` cannot be 0.2Hz or slower!)
+The outputs will begin firing automatically when clock signals are received on `din`, and will stop
+if the input signals are stopped for 5s or longer.  Upon stopping all output channels will reset.
+(NOTE: this means the signal coming into `din` cannot be 0.2Hz or slower!)
 
 Applying a signal of at least 0.8V to `ain` will reset all output channels.
 
 ## Persistence
 
-The clock modifiers for output channels 1 and 4 are read directly from the positions of `k1` and `k2` on startup.
-The modifiers for the other channels (2, 3, 5, and 6) are saved in a configuration file and will persist across
-restarts.
+The clock modifiers for output channels 1 and 4 are read directly from the positions of `k1` and
+`k2` on startup. The modifiers for the other channels (2, 3, 5, and 6) are saved in a configuration
+file and will persist across restarts.
 
 ## Note on Phase Alignment
 
-Changing the clock modifers while the module is running is possible, but can (and generally will) result in some
-phase-shifting of the outputs. e.g. if `cv1` and `cv2` are set to `x1`, changing `cv1` to `x2` and then back to `x1`
-will probably result in `cv1` and `cv2` no longer being synchronized.
+Changing the clock modifers while the module is running is possible, but can (and generally will)
+result in some phase-shifting of the outputs. e.g. if `cv1` and `cv2` are set to `x1`, changing
+`cv1` to `x2` and then back to `x1` will probably result in `cv1` and `cv2` no longer being
+synchronized.
 
-This can be mitigated either by not adjusting the clock modifers while the module is running, or by patching a reset
-signal into `ain` to force the module to re-synchronize periodically.  Alternatively, embrace the chaos and use the
-de-syncronization as a performance effect.
+This can be mitigated either by not adjusting the clock modifers while the module is running, or by
+patching a reset signal into `ain` to force the module to re-synchronize periodically.
+Alternatively, embrace the chaos and use the de-syncronization as a performance effect.

software/contrib/coin_toss.md

@@ -1,12 +1,22 @@
 # Coin Toss
 
-author: awonak
+Two pairs of clocked probability gates.
 
-date: 03/01/22
+## Inputs & Outputs
 
-labels: Clock, Random, CV Generation
+Inputs:
+- `din`: External clock (when in external clock mode)
+- `ain`: Threshold control (summed with threshold knob)
+- `k1`: internal clock speed
+- `k2`: probability threshold
+- `b1`: toggle internal / external clock source
+- `b2`: toggle gate/trigger mode
 
-Two pairs of clocked probability gates.
+Outputs:
+- `cv1` & `cv2`: Coin 1 gate output pair when voltage above/below threshold
+- `cv3`: Coin 1 clock
+- `cv4` & `cv5`: Coin 2 gate output pair at 1/4x speed
+- `cv6`: Coin 2 clock
 
 Knob 1 adjusts the master clock speed of gate change probability. Knob 2 moves
 the probability thresholed between A and B with a 50% chance at noon. Output
@@ -15,23 +25,3 @@ row 1 (cv1 and cv2) run at 1x speed and output row 2 (cv4 and cv5) run at
 internal and external clock source. Push button 2 to toggle between gate and
 trigger mode. Analogue input is summed with the threshold knob value to allow
 external threshold control.
-
-    digital in: External clock (when in external clock mode)
-    analogue in: Threshold control (summed with threshold knob)
-    knob 1: internal clock speed
-    knob 2: probability threshold
-    button 1: toggle internal / external clock source
-    button 2: toggle gate/trigger mode
-    cv1/cv2: Coin 1 gate output pair when voltage above/below threshold
-    cv4/cv5: Coin 2 gate output pair at 1/4x speed
-    cv3: Coin 1 clock
-    cv6: Coin 2 clock
-
-For developing, I like to use Visual Studio Code as my IDE and `rshell` to copy
-and run my scripts.
-
-From the root dir of the repo, enter rshell:
-
-    $ rshell
-    > cp software/contrib/coin_toss.py /pyboard/main.py
-    > repl pyboard ~ import main