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Opcodes v1
This is Version 1 of the CPU design, which is now out-of-date.
The CPU will use fixed-length 16-bit instructions. The opcode is in the MSB and the operand is in the LSB.
Bits 7 and 6 (gg) of the opcode indicate the instruction group:
00 - Data movement: (ALU not required): LOAD, STOR, PUSH, POPP
01 - Data manipulation: ADDD, SUBB, COMP, ANDD, ORRR, NOTT, XORR, NAND, NORR, SHxx, Rxxx
10 - Bit operations: BITS, BITC, SETx, CLRx
11 - Program control: JUMP, JPxx, HALT, NOOP
Bits 5 to 0 depend on the instruction group.
Bits 5 to 3 (mmm) indicate the movement type:
000 - LOAD Immediate
001 - LOAD Direct
010 - LOAD Register
011 - STOR Direct
100 - STOR Register
101 - PUSH Register
110 - PUSH Immediate
111 - POPP Register
Bits 2 to 0 (rrr) depend on the addressing mode.
- For Register addressing mode, the bits select the register (source for
LOADandPUSH, destination forSTORandPOPP):
000 - AC
001 - FL
010 - SH
011 - SL
100 - MH
101 - JH
110 - JL
- For other addressing modes, the
rrrbits are unused.
Bit 5 (m) indicates the addressing mode:
0 - Immediate
1 - Indirect
Bits 4 to 1 (iiii) select the specific operation.
Bit 0 is unused.
Bit 5 (r) selects the register that is being operated on:
0 - AC
1 - FL
Bit 4 (v) selects the value (1 for set or 0 for clear) of the operation.
Bits 3 to 1 (bbb) select the bit position that is updated.
Bit 0 is unused.
Bit 5 (u) selects whether the operation is unconditional or conditional.
Bits 4 to 1 (jjjj) select the specific operation.
Bit 0 is unused.
Opcodes which are not listed are reserved for future use. Functionality of unlisted opcodes should not be assumed to work the same in future iterations of the CPU.
Data Movement Instructions
Bit fields
Opcode Mnemonic Mode 00 mmm rrr
------ --------- ---- ------------
00 LOAD #dd IMM 00 000 000
08 LOAD (mm) DIR 00 001 000
10 LOAD AC REG 00 010 000
11 LOAD FL REG 00 010 001
12 LOAD SH REG 00 010 010
13 LOAD SL REG 00 010 011
14 LOAD MH REG 00 010 100
15 LOAD JH REG 00 010 101
16 LOAD JL REG 00 010 110
18 STOR (mm) DIR 00 011 000
20 STOR AC REG 00 100 000
21 STOR FL REG 00 100 001
22 STOR SH REG 00 100 010
23 STOR SL REG 00 100 011
24 STOR MH REG 00 100 100
25 STOR JH REG 00 100 101
26 STOR JL REG 00 100 110
28 PUSH AC REG 00 101 000
29 PUSH FL REG 00 101 001
2A PUSH SH REG 00 101 010
2B PUSH SL REG 00 101 011
2C PUSH MH REG 00 101 100
2D PUSH JH REG 00 101 101
2E PUSH JL REG 00 101 110
30 PUSH #dd IMM 00 110 000
38 POPP AC REG 00 111 000
39 POPP FL REG 00 111 001
3A POPP SH REG 00 111 010
3B POPP SL REG 00 111 011
3C POPP MH REG 00 111 100
3D POPP JH REG 00 111 101
3E POPP JL REG 00 111 110
Data Manipulation Instructions
Bit fields
Opcode Mnemonic Mode 01 m iiii x
------ --------- ---- ------------
40 COMP #dd IMM 01 0 0000 0
42 SUBB #dd IMM 01 0 0001 0
44 ADDD #dd IMM 01 0 0010 0
50 ANDD #dd IMM 01 0 1000 0
52 ORRR #dd IMM 01 0 1001 0
54 XORR #dd IMM 01 0 1010 0
56 NAND #dd IMM 01 0 1011 0
58 NORR #dd IMM 01 0 1100 0
60 NOTT IND 01 1 0000 0
70 SHRL IND 01 1 1000 0
72 SHLL IND 01 1 1001 0
74 SHRA IND 01 1 1010 0
78 ROTR IND 01 1 1100 0
7A RRTC IND 01 1 1101 0
7C ROTL IND 01 1 1110 0
7E RLTC IND 01 1 1111 0
Bit Operation Instructions
Bit fields
Opcode Mnemonic Mode 10 r v bbb y
------ --------- ---- ------------
80 BITC 0 BIT 10 0 0 000 0
82 BITC 1 BIT 10 0 0 001 0
84 BITC 2 BIT 10 0 0 010 0
86 BITC 3 BIT 10 0 0 011 0
88 BITC 4 BIT 10 0 0 100 0
8A BITC 5 BIT 10 0 0 101 0
8C BITC 6 BIT 10 0 0 110 0
8E BITC 7 BIT 10 0 0 111 0
90 BITS 0 BIT 10 0 1 000 0
92 BITS 1 BIT 10 0 1 001 0
92 BITS 2 BIT 10 0 1 010 0
92 BITS 3 BIT 10 0 1 011 0
92 BITS 4 BIT 10 0 1 100 0
92 BITS 5 BIT 10 0 1 101 0
92 BITS 6 BIT 10 0 1 110 0
92 BITS 7 BIT 10 0 1 111 0
A0 CLRV BIT 10 1 0 000 0
A2 CLRS BIT 10 1 0 001 0
A4 CLRC BIT 10 1 0 010 0
A6 CLRZ BIT 10 1 0 011 0
B0 SETV BIT 10 1 1 000 0
B2 SETS BIT 10 1 1 001 0
B4 SETC BIT 10 1 1 010 0
B6 SETZ BIT 10 1 1 011 0
Program Control Instructions
Bit fields
Opcode Mnemonic Mode 11 u jjjj z
------ --------- ---- ------------
C0 JPVC #aa IMM 11 0 0000 0
C2 JPSC #aa IMM 11 0 0001 0
C4 JPCC #aa IMM 11 0 0010 0
C6 JPZC #aa IMM 11 0 0011 0
D0 JPVS #aa IMM 11 0 1000 0
D2 JPSS #aa IMM 11 0 1001 0
D4 JPCS #aa IMM 11 0 1010 0
D6 JPZS #aa IMM 11 0 1011 0
E0 JUMP #aa IMM 11 1 0000 0
E6 JUMP JL REG 11 1 0011 0 ; This only works with the `JL` register
FC NOOP N/A 11 1 1110 0
FF HALT N/A 11 1 1111 1
Note that the opcode for HALT was intentionally chosen to be 0xFF.
| Date | Changes |
|---|---|
| 02-Oct-2025 | Created |
| 09-Oct-2025 | Opcode cleanup. Some values changed. |