init

Signed-off-by: Yanheng Lu <yanheng.lyh@alibaba-inc.com>

Author: flyingegret2018

README.md

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+<h1 align="center">CHAM</h1>
+<h4 align="center">A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product</h4>
+
+The __CHAM__ project is initiated by Alibaba DAMO Academy CTL and Ant Group's AntChain.
+
+___CHAM___ is a customized homomorphic encryption accelerator for fast matrix-vector product. Homomorphic encryption (HE), enabling computation on encrypted data, suffers from poor performance due to enlarged data size and exploded amount of computation. Existing HE accelerators either target small HE operations or fail to support fast-evolving HE algorithms. To better support various privacy-preserving applications (e.g., logistic regression and neural-network inference), we propose CHAM for high-performance matrix-vector product, which can be easily extended to 2D/3D convolutions. 
+
+The code in this repository is released by Alibaba DAMO Academy CTL and Ant Group's AntChain under MIT License.
+
+The distribution is developed as part of our DAC2023 paper called *"CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product"*. This distribution is an open-source version of our commercial accelerator and not ready for production use.
+
+
+## Table of contents
+
+- [Directory structure](#directory-structure)
+- [Build guide](#build-guide)
+- [License](#license)
+
+## Directory structure
+
+The directory structure is as follows:
+
+* [__src__](src): RTL source files
+* [__include__](include): include files
+* [__sim__](sim): simulation environment
+* [__tv__](tv): test vectors
+* [__xilinx_vcs_lib__](xilinx_vcs_lib): xilinx vcs simulation library
+
+
+## Build guide
+
+1. Generate xilinx vcs lib in ./xilinx_vcs_lib
+2. Modify sim/vcs/tb_top.sh line 48 to your vcs path
+3. cd sim
+4. make clean //remove the previous run_dir
+5. ./run_case <test name>//test name is showing below in Test cases
+    test_stg_0_0                test single stage at stage 0, and test only ksk ram init path
+    test_stg_0_1                test single stage at stage 0, and test only preprocess init path
+    test_stg_1                  test single stage at stage 1
+    test_stg_2                  test single stage at stage 2
+    test_stg_3                  test single stage at stage 3
+    test_stg_4                  test single stage at stage 4
+    test_stg_5                  test single stage at stage 5
+    test_stg_6                  test single stage at stage 6
+    test_stg_7                  test single stage at stage 7
+    test_stg_8                  test single stage at stage 8
+    test_stg_9                  test single stage at stage 9
+    test_stg_10                 test single stage at stage 10
+    test_row                    test all stages in a row
+    test_full_no_uram_4x4096    test full case, the test vector is 4x4096. we use testbench to init ksk ram instead of designtest_full_4x4096            test full case, the test vector is 4x4096.
+    test_full_4x4096            test full case, the test vector is 4x4096.
+
+## License
+
+[MIT License](LICENSE)
+
+This product contains several third-party components under other open source licenses.
+
+    src/axi/axi_read_master.sv          BSD-2-Clause        Vitis-Tutorials
+    src/axi/axi_write_master.sv         BSD-2-Clause        Vitis-Tutorials
+    src/axi/counter.sv                  BSD-2-Clause        Vitis-Tutorials

include/addx_defines.vh

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+`timescale 1ns/1ps

include/common_defines.vh

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+//////////////////////////////////////////////////
+// Author: Zhang Yichi (changlv)
+// Email: changlv.zyc@alibaba-inc.com
+//
+// Project Name: MVP
+// Module Name: common_defines
+// Modify Date: 07/08/2021 13:00
+// Description: Attributes of common modules (modadd, modsub, etc.)
+//////////////////////////////////////////////////
+
+`ifndef __COMMON_DEFINES_VH__
+`define __COMMON_DEFINES_VH__
+
+`timescale 1ns/1ps
+
+//`define SIMULATION
+`define FPGA
+
+
+`define COMMON_DATA_LENGTH      4096
+`define COMMON_BRAM_DELAY       1       // delay of Block RAM
+`define COMMON_URAM_DELAY       3       // delay of Ultra RAM
+`define COMMON_MODMUL_DELAY     4       // delay of ModMul module
+`define COMMON_MODADD_DELAY     1       // delay of ModAdd module
+`define COMMON_MODSUB_DELAY     1       // delay of ModSub module
+`define COMMON_MODSUBRED_DELAY  2       // delay of ModSubRed module
+
+`endif // __COMMON_DEFINES_VH__

include/dp_defines.vh

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+//////////////////////////////////////////////////
+// Author: Gu Zhen (jingchen)
+// Email: guzhen.gz@alibaba-inc.com
+//
+// Project Name: MVP
+// Module Name: dp_defines
+// Modify Date: 12/03/2022 13:00
+// Description: Attributes of dp modules
+//////////////////////////////////////////////////
+
+`ifndef __DP_DEFINES_VH__
+`define __DP_DEFINES_VH__
+
+`timescale 1ns/100ps
+
+//`define SIMULATION
+`define FPGA
+
+`define COMMON_DATA_LENGTH      4096
+`define COMMON_BRAM_DELAY       1       // delay of Block RAM
+`define COMMON_URAM_DELAY       1       // delay of Ultra RAM
+`define COMMON_MODMUL_DELAY     4       // delay of ModMul module
+`define COMMON_MODADD_DELAY     1       // delay of ModAdd module
+`define COMMON_MODSUB_DELAY     1       // delay of ModSub module
+`define COMMON_MODSUBRED_DELAY  2       // delay of ModSubRed module
+`define COMMON_MODMULADD_DELAY  4       // delay of ModMulAdd module
+`define DP_MADD_PIP_DELAY       5
+`define NUM_BASE_BANK           8
+`define COE_WIDTH_0             35
+`define COE_WIDTH_1             35
+`define COE_WIDTH_2             39
+`define N 4096
+`define BRAM_DEPTH 512
+`define  Q0 17314086913    // Q35 0
+`define  Q1 17180393473    // Q35 1
+`define  Q2 274886295553  // Q39
+`define  Qinv0 17309859841
+`define  Qinv1 17176199041
+`define  Qinv2 274819184641
+`define MAX_N_SPLIT 4
+`define NUM_CTXT    2
+`define NUM_MOD     3
+`endif // __DP_DEFINES_VH__

include/monox_defines.vh

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+`timescale 1ns / 1ps

include/mux_defines.vh

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+`timescale 1ns / 1ps

include/ntt_intt_defines.vh

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+//////////////////////////////////////////////////
+// Engineer: Chen Zhaohui (xinming)
+// Email: chenzhaohui.czh@alibaba-inc.com
+//
+// Project Name: MVP
+// Module Name: ntt_intt_defines
+// Modify Date: 07/28/2021 11:10
+
+// Description: Define timescale and some common params
+//////////////////////////////////////////////////
+
+`include "common_defines.vh"
+`ifndef __NTT_INTT_DEFINES_VH__
+`define __NTT_INTT_DEFINES_VH__
+
+`define N 4096
+`define  Q0 17314086913    // Q35 0
+`define  Q1 17180393473    // Q35 1
+`define  Q2 274886295553  // Q39
+
+`endif // __NTT_INTT_DEFINES_VH__

include/vpu2_defines.vh

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+//////////////////////////////////////////////////
+// Author: Zhang Yichi (changlv)
+// Email: changlv.zyc@alibaba-inc.com
+//
+// Project Name: MVP
+// Module Name: vpu2_defines 
+// Modify Date: 07/09/2021 16:30
+//
+// Description: Attributes and parameters of VPU2
+//////////////////////////////////////////////////
+
+`ifndef __VPU2_DEFINES_VH__
+`define __VPU2_DEFINES_VH__
+
+`define VPU2_DELAY     (`COMMON_URAM_DELAY + `COMMON_MODMUL_DELAY + `COMMON_MODADD_DELAY)
+
+`define VPU2_RD_BEGIN  0
+`define VPU2_WR_BEGIN  (`VPU2_RD_BEGIN + `VPU2_DELAY)
+
+`define VPU2_RD_END    (`VPU2_RD_BEGIN + `COMMON_DATA_LENGTH)
+`define VPU2_WR_END    (`VPU2_WR_BEGIN + `COMMON_DATA_LENGTH)
+
+`define VPU2_BUSY_END  (`VPU2_WR_END)   // when state BUSY -> IDLE
+
+`endif // __VPU2_DEFINES_VH__

include/vpu3_defines.vh

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+//////////////////////////////////////////////////
+// Author: Zhang Yichi (changlv)
+// Email: changlv.zyc@alibaba-inc.com
+//
+// Project Name: MVP
+// Module Name: VPU3
+// Modify Date: 07/14/2021 15:30
+//
+// Description: Attributes and parameters of VP3U
+//////////////////////////////////////////////////
+
+`ifndef __VPU3_DEFINES_VH__
+`define __VPU3_DEFINES_VH__
+
+`define VPU3_DELAY      (`COMMON_BRAM_DELAY + `COMMON_MODADD_DELAY + `COMMON_MODSUBRED_DELAY + `COMMON_MODSUB_DELAY + `COMMON_MODMUL_DELAY + `COMMON_MODADD_DELAY)
+
+`define VPU3_RD_BEGIN   0
+`define VPU3_RDA_BEGIN  (`VPU3_RD_BEGIN + `COMMON_MODADD_DELAY + `COMMON_MODSUBRED_DELAY)
+`define VPU3_RDB_BEGIN  (`VPU3_RD_BEGIN + `COMMON_MODADD_DELAY + `COMMON_MODSUBRED_DELAY + `COMMON_MODSUB_DELAY + `COMMON_MODMUL_DELAY)
+`define VPU3_RDC_BEGIN  (`VPU3_RD_BEGIN + 0)
+`define VPU3_WR_BEGIN   (`VPU3_RD_BEGIN + `VPU3_DELAY)
+
+`define VPU3_RD_END     (`VPU3_RD_BEGIN + `COMMON_DATA_LENGTH)
+`define VPU3_RDA_END    (`VPU3_RDA_BEGIN + `COMMON_DATA_LENGTH)
+`define VPU3_RDB_END    (`VPU3_RDB_BEGIN + `COMMON_DATA_LENGTH)
+`define VPU3_RDC_END    (`VPU3_RDC_BEGIN + `COMMON_DATA_LENGTH)
+`define VPU3_WR_END     (`VPU3_WR_BEGIN + `COMMON_DATA_LENGTH)
+
+`define VPU3_BUSY_END   (`VPU3_WR_END)   // when state BUSY -> IDLE
+
+`endif // __VPU3_DEFINES_VH__
+

include/vpu4_defines.vh

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+//////////////////////////////////////////////////
+// Author: Zhang Yichi (changlv)
+// Email: changlv.zyc@alibaba-inc.com
+//
+// Project Name: MVP
+// Module Name: vpu4_defines
+// Modify Date: 07/14/2021 16:00
+// Description: Attributes and parameters of VPU4
+//////////////////////////////////////////////////
+
+`ifndef __VPU4_DEFINES_VH__
+`define __VPU4_DEFINES_VH__
+
+`define VPU4_DELAY      (`COMMON_BRAM_DELAY + `COMMON_MODSUB_DELAY + `COMMON_MODMUL_DELAY)
+
+`define VPU4_RD_BEGIN   0
+`define VPU4_WR_BEGIN   (`VPU4_RD_BEGIN + `VPU4_DELAY)
+
+`define VPU4_RD_END     (`VPU4_RD_BEGIN + `COMMON_DATA_LENGTH)
+`define VPU4_WR_END     (`VPU4_WR_BEGIN + `COMMON_DATA_LENGTH)
+
+`define VPU4_BUSY_END   (`VPU4_WR_END)   // when state BUSY -> IDLE
+
+`endif // __VPU4_DEFINES_VH__
+