Skip to content

Commit c2b1e4d

Browse files
flyingegret2018flyingegret2018
committed
chisel source file added
Signed-off-by: Yanheng Lu <yanheng.lyh@alibaba-inc.com>
1 parent 960bf22 commit c2b1e4d

18 files changed

Lines changed: 944 additions & 0 deletions

‎chisel/build.sbt‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
// See README.md for license details.
2+
3+
ThisBuild / scalaVersion := "2.13.7"
4+
ThisBuild / version := "0.1.0"
5+
ThisBuild / organization := "com.github.ycvertex"
6+
7+
val chiselVersion = "3.5.2"
8+
9+
lazy val root = (project in file("."))
10+
.settings(
11+
name := "chisel-test",
12+
libraryDependencies ++= Seq(
13+
"edu.berkeley.cs" %% "chisel3" % chiselVersion,
14+
"edu.berkeley.cs" %% "chiseltest" % "0.5.0-RC2" % "test",
15+
"edu.berkeley.cs" %% "chisel-iotesters" % "2.5.0-RC2"
16+
),
17+
scalacOptions ++= Seq(
18+
"-language:reflectiveCalls",
19+
"-deprecation",
20+
"-feature",
21+
"-Xcheckinit",
22+
),
23+
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full),
24+
)
25+

‎chisel/build.sc‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
// import Mill dependency
2+
import mill._
3+
import mill.define.Sources
4+
import mill.modules.Util
5+
import mill.scalalib.TestModule.ScalaTest
6+
import scalalib._
7+
// support BSP
8+
import mill.bsp._
9+
10+
object chisel-test extends SbtModule { m =>
11+
override def millSourcePath = os.pwd
12+
override def scalaVersion = "2.12.13"
13+
override def scalacOptions = Seq(
14+
"-Xsource:2.11",
15+
"-language:reflectiveCalls",
16+
"-deprecation",
17+
"-feature",
18+
"-Xcheckinit",
19+
// Enables autoclonetype2 in 3.4.x (on by default in 3.5)
20+
"-P:chiselplugin:useBundlePlugin"
21+
)
22+
override def ivyDeps = Agg(
23+
ivy"edu.berkeley.cs::chisel3:3.4.3",
24+
)
25+
override def scalacPluginIvyDeps = Agg(
26+
ivy"edu.berkeley.cs:::chisel3-plugin:3.4.3",
27+
ivy"org.scalamacros:::paradise:2.1.1"
28+
)
29+
object test extends Tests with ScalaTest {
30+
override def ivyDeps = m.ivyDeps() ++ Agg(
31+
ivy"edu.berkeley.cs::chiseltest:0.3.3"
32+
)
33+
}
34+
}

‎chisel/project/build.properties‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
sbt.version = 1.4.9

‎chisel/project/plugins.sbt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
logLevel := Level.Warn

‎chisel/readme‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
Attention: chisel environment is ready in cs01-cs04!
2+
3+
1. Please run the following command in this path to generate the new source file
4+
sbt "test:runMain GenPreprocess"
5+
6+
2. Then copy the generated file to src path
7+
cp generated/preprocess/preprocess_top_chisel.v ../src/preprocess/preprocess_top_chisel.v
8+
9+
3. Run simulation to check the result
10+
11+
The first run may need several minutes. And then maybe 30 seconds to generate the RTL.

‎chisel/src/main/scala/Buffer.scala‎

Lines changed: 158 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,158 @@
1+
package mvp.buffer
2+
3+
import chisel3._
4+
import chisel3.util._
5+
import chisel3.experimental._
6+
7+
import mvp.common._
8+
import mvp.polyram._
9+
10+
class poly_rd_interface(width: Int, nElems: Int, nBanks: Int, readDelay: Int) extends Module {
11+
override val desiredName = s"poly_rd_interface_${width}_${nElems}_${nBanks}_${readDelay}"
12+
13+
val dataWidth = width
14+
val hiAddrWidth = utils.log2(nBanks)
15+
val loAddrWidth = utils.log2(nElems)
16+
val addrWidth = hiAddrWidth + loAddrWidth
17+
18+
val io = IO(new Bundle {
19+
val vpu_rd = Flipped(new VpuRdPort(dataWidth, addrWidth, nBanks))
20+
val buf_rd = new BufRdPort(dataWidth, loAddrWidth, nBanks)
21+
})
22+
23+
val lo_addr = utils.slice(io.vpu_rd.addr, 0, loAddrWidth)
24+
val hi_addr = utils.slice(io.vpu_rd.addr, loAddrWidth, addrWidth)
25+
26+
io.buf_rd.addr := utils.repeat(nBanks, lo_addr)
27+
28+
var lut = List.tabulate(nBanks) { x => (x.U -> io.buf_rd.data(x)) }
29+
30+
io.vpu_rd.data := MuxLookup(ShiftRegister(hi_addr, readDelay), 0.U, lut)
31+
}
32+
33+
class poly_wr_interface(width: Int, nElems: Int, nBanks: Int) extends Module {
34+
override val desiredName = s"poly_wr_interface_${width}_${nElems}_${nBanks}"
35+
36+
val dataWidth = width
37+
val hiAddrWidth = utils.log2(nBanks)
38+
val loAddrWidth = utils.log2(nElems)
39+
val addrWidth = hiAddrWidth + loAddrWidth
40+
41+
val io = IO(new Bundle {
42+
val vpu_wr = Flipped(new VpuWrPort(dataWidth, addrWidth, nBanks))
43+
val buf_wr = new BufWrPort(dataWidth, loAddrWidth, nBanks)
44+
})
45+
46+
val lo_addr = utils.slice(io.vpu_wr.addr, 0, loAddrWidth)
47+
val hi_addr = utils.slice(io.vpu_wr.addr, loAddrWidth, addrWidth)
48+
49+
io.buf_wr.addr := utils.repeat(nBanks, lo_addr)
50+
io.buf_wr.data := utils.repeat(nBanks, io.vpu_wr.data)
51+
52+
when (io.vpu_wr.en) {
53+
io.buf_wr.en := UIntToOH(hi_addr).asBools
54+
} .otherwise {
55+
io.buf_wr.en := utils.repeat(nBanks, 0.B)
56+
}
57+
}
58+
59+
class double_pp_buffer(width: Int, nElems: Int, nBanks: Int) extends Module {
60+
override val desiredName = s"double_pp_buffer_${width}_${nElems}_${nBanks}"
61+
62+
val io = IO(new Bundle {
63+
val i_done = Input(Bool())
64+
val polyvec0_rd = Flipped(new BufRdPort(width, utils.log2(nElems), nBanks))
65+
val polyvec0_wr = Flipped(new BufWrPort(width, utils.log2(nElems), nBanks))
66+
val polyvec1_rd = Flipped(new BufRdPort(width, utils.log2(nElems), nBanks))
67+
val polyvec1_wr = Flipped(new BufWrPort(width, utils.log2(nElems), nBanks))
68+
})
69+
70+
val done_r = RegNext(io.i_done)
71+
72+
val s01 :: s10 :: Nil = Enum(2)
73+
val state = RegInit(s01)
74+
when (io.i_done && !done_r) {
75+
switch (state) {
76+
is (s01) { state := s10 }
77+
is (s10) { state := s01 }
78+
}
79+
}
80+
81+
val u_ram = List.fill(2) {
82+
Module(new poly_ram_wrapper(width, utils.log2(nElems), nBanks))
83+
}
84+
85+
when (state === s01) {
86+
io.polyvec0_rd <> u_ram(0).io.rd
87+
io.polyvec0_wr <> u_ram(0).io.wr
88+
io.polyvec1_rd <> u_ram(1).io.rd
89+
io.polyvec1_wr <> u_ram(1).io.wr
90+
} .elsewhen (state === s10) {
91+
io.polyvec0_rd <> u_ram(1).io.rd
92+
io.polyvec0_wr <> u_ram(1).io.wr
93+
io.polyvec1_rd <> u_ram(0).io.rd
94+
io.polyvec1_wr <> u_ram(0).io.wr
95+
} .otherwise {
96+
io := DontCare
97+
u_ram(0).io := DontCare
98+
u_ram(1).io := DontCare
99+
}
100+
}
101+
102+
class triple_pp_buffer(width: Int, nElems: Int, nBanks: Int) extends Module {
103+
override val desiredName = s"triple_pp_buffer_${width}_${nElems}_${nBanks}"
104+
105+
val io = IO(new Bundle {
106+
val i_done = Input(Bool())
107+
val polyvec0_rd = Flipped(new BufRdPort(width, utils.log2(nElems), nBanks))
108+
val polyvec0_wr = Flipped(new BufWrPort(width, utils.log2(nElems), nBanks))
109+
val polyvec1_rd = Flipped(new BufRdPort(width, utils.log2(nElems), nBanks))
110+
val polyvec1_wr = Flipped(new BufWrPort(width, utils.log2(nElems), nBanks))
111+
val polyvec2_rd = Flipped(new BufRdPort(width, utils.log2(nElems), nBanks))
112+
val polyvec2_wr = Flipped(new BufWrPort(width, utils.log2(nElems), nBanks))
113+
})
114+
115+
val done_r = RegNext(io.i_done)
116+
117+
val s012 :: s201 :: s120 :: Nil = Enum(3)
118+
val state = RegInit(s012)
119+
when (io.i_done && !done_r) {
120+
switch (state) {
121+
is (s012) { state := s201 }
122+
is (s201) { state := s120 }
123+
is (s120) { state := s012 }
124+
}
125+
}
126+
127+
val u_ram = List.fill(3) {
128+
Module(new poly_ram_wrapper(width, utils.log2(nElems), nBanks))
129+
}
130+
131+
when (state === s012) {
132+
io.polyvec0_rd <> u_ram(0).io.rd
133+
io.polyvec0_wr <> u_ram(0).io.wr
134+
io.polyvec1_rd <> u_ram(1).io.rd
135+
io.polyvec1_wr <> u_ram(1).io.wr
136+
io.polyvec2_rd <> u_ram(2).io.rd
137+
io.polyvec2_wr <> u_ram(2).io.wr
138+
} .elsewhen (state === s201) {
139+
io.polyvec0_rd <> u_ram(2).io.rd
140+
io.polyvec0_wr <> u_ram(2).io.wr
141+
io.polyvec1_rd <> u_ram(0).io.rd
142+
io.polyvec1_wr <> u_ram(0).io.wr
143+
io.polyvec2_rd <> u_ram(1).io.rd
144+
io.polyvec2_wr <> u_ram(1).io.wr
145+
} .elsewhen (state === s120) {
146+
io.polyvec0_rd <> u_ram(1).io.rd
147+
io.polyvec0_wr <> u_ram(1).io.wr
148+
io.polyvec1_rd <> u_ram(2).io.rd
149+
io.polyvec1_wr <> u_ram(2).io.wr
150+
io.polyvec2_rd <> u_ram(0).io.rd
151+
io.polyvec2_wr <> u_ram(0).io.wr
152+
} .otherwise {
153+
io := DontCare
154+
u_ram(0).io := DontCare
155+
u_ram(1).io := DontCare
156+
u_ram(2).io := DontCare
157+
}
158+
}

0 commit comments

Comments
 (0)