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Update Corstone board layer for GCC
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Alif/AppKit/Board/Corstone-300/Board-U55.clayer.yml

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linker:
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- script: ./mps3-sse-300.sct
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for-compiler: AC6
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- script: ./RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src
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regions: ./RTE/Device/SSE-300-MPS3/regions_V2M-MPS3-SSE-300-FVP.h
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for-compiler: GCC

Alif/AppKit/Board/Corstone-300/Board-U65.clayer.yml

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linker:
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- script: ./mps3-sse-300.sct
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for-compiler: AC6
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- script: ./RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src
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regions: ./RTE/Device/SSE-300-MPS3/regions_V2M-MPS3-SSE-300-FVP.h
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for-compiler: GCC

Alif/AppKit/Board/Corstone-300/Board.clayer.yml

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linker:
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- script: ./mps3-sse-300.sct
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for-compiler: AC6
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- script: ./RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src
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regions: ./RTE/Device/SSE-300-MPS3/regions_V2M-MPS3-SSE-300-FVP.h
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for-compiler: GCC
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/*
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* Copyright (c) 2023 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------------
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Stack seal size definition
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*----------------------------------------------------------------------------*/
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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#define __STACKSEAL_SIZE ( 8 )
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#else
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#define __STACKSEAL_SIZE ( 0 )
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#endif
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/* ----------------------------------------------------------------------------
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Memory definition
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*----------------------------------------------------------------------------*/
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MEMORY
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{
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ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
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#if __ROM1_SIZE > 0
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ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
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#endif
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#if __ROM2_SIZE > 0
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ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
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#endif
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#if __ROM3_SIZE > 0
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ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
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#endif
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RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
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#if __RAM1_SIZE > 0
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RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
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#endif
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#if __RAM2_SIZE > 0
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RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
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#endif
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#if __RAM3_SIZE > 0
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RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
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#endif
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __copy_table_start__
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* __copy_table_end__
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* __zero_table_start__
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* __zero_table_end__
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* __etext (deprecated)
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __noinit_start
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* __noinit_end
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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KEEP(*(.vectors))
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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KEEP(*(.eh_frame*))
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} > ROM0
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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.gnu.sgstubs :
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{
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. = ALIGN(32);
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} > ROM0
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#endif
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > ROM0
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > ROM0
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__exidx_end = .;
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (LOADADDR(.data))
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LONG (ADDR(.data))
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LONG (SIZEOF(.data) / 4)
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/* Add each additional data section here */
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/*
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LONG (LOADADDR(.data2))
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LONG (ADDR(.data2))
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LONG (SIZEOF(.data2) / 4)
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*/
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__copy_table_end__ = .;
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} > ROM0
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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/* .bss initialization to zero is already done during C Run-Time Startup.
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LONG (ADDR(.bss))
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LONG (SIZEOF(.bss) / 4)
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*/
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/* Add each additional bss section here */
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/*
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LONG (ADDR(.bss2))
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LONG (SIZEOF(.bss2) / 4)
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*/
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__zero_table_end__ = .;
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} > ROM0
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/*
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* This __etext variable is kept for backward compatibility with older,
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* ASM based startup files.
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*/
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PROVIDE(__etext = LOADADDR(.data));
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.data : ALIGN(4)
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{
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__data_start__ = .;
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*(vtable)
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*(.data)
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*(.data.*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > RAM0 AT > ROM0
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/*
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* Secondary data section, optional
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*
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* Remember to add each additional data section
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* to the .copy.table above to assure proper
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* initialization during startup.
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*/
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/*
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.data2 : ALIGN(4)
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{
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. = ALIGN(4);
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__data2_start__ = .;
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*(.data2)
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*(.data2.*)
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. = ALIGN(4);
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__data2_end__ = .;
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} > RAM1 AT > ROM0
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*/
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.bss :
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{
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > RAM0 AT > RAM0
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/*
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* Secondary bss section, optional
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*
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* Remember to add each additional bss section
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* to the .zero.table above to assure proper
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* initialization during startup.
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*/
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/*
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.bss2 :
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{
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. = ALIGN(4);
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__bss2_start__ = .;
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*(.bss2)
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*(.bss2.*)
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. = ALIGN(4);
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__bss2_end__ = .;
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} > RAM1 AT > RAM1
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*/
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/* This section contains data that is not initialized during load,
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or during the application's initialization sequence. */
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.noinit (NOLOAD) :
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{
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. = ALIGN(4);
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__noinit_start = .;
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*(.noinit)
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*(.noinit.*)
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. = ALIGN(4);
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__noinit_end = .;
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} > RAM0
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.heap (NOLOAD) :
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{
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. = ALIGN(8);
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__end__ = .;
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PROVIDE(end = .);
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. = . + __HEAP_SIZE;
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. = ALIGN(8);
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__HeapLimit = .;
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} > RAM0
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.stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
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{
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. = ALIGN(8);
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__StackLimit = .;
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. = . + __STACK_SIZE;
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. = ALIGN(8);
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__StackTop = .;
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} > RAM0
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PROVIDE(__stack = __StackTop);
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#if __STACKSEAL_SIZE > 0
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.stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
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{
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. = ALIGN(8);
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__StackSeal = .;
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. = . + 8;
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. = ALIGN(8);
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} > RAM0
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#endif
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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}

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