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Introduction to the Arm RD‑V3 Platform

This module introduces the Arm Neoverse CSS‑V3 architecture and the RD‑V3 Reference Design Platform Software that implements it. You'll learn how these components enable scalable, server-class system design, and how to simulate and validate the full firmware stack using Fixed Virtual Platforms (FVP)—well before hardware is available.

Arm Neoverse is designed to meet the demanding requirements of data center and edge computing, delivering high performance and efficiency. Widely adopted in servers, networking, and edge devices, the Neoverse architecture provides a solid foundation for modern infrastructure.

Using Arm Fixed Virtual Platforms (FVPs), you can explore system bring-up, boot flow, and firmware customization well before physical silicon becomes available.

This module also introduces the key components involved, from Neoverse V3 cores to secure subsystem controllers, and shows how these elements work together in a fully virtualized system simulation.

Neoverse CSS-V3 Platform Overview

Neoverse CSS-V3 (Compute Subsystem Version 3) is the core subsystem architecture underpinning the Arm RD-V3 platform. It is specifically optimized for high-performance server and data center applications, providing a highly integrated solution combining processing cores, memory management, and interconnect technology.

CSS V3 forms the key building block for specialized computing systems. It reduces design and validation costs for the general-purpose compute subsystem, allowing partners to focus on their specialization and acceleration while reducing risk and accelerating time to deployment.

CSS‑V3 is available in configurable subsystems, supporting up to 64 Neoverse V3 cores per die. It also enables integration of high-bandwidth DDR5/LPDDR5 memory (up to 12 channels), PCIe Gen5 or CXL I/O (up to 64 lanes), and high-speed die-to-die links with support for UCIe 1.1 or custom PHYs. Designs can be scaled down to smaller core-count configurations, such as 32-core SoCs, or expanded through multi-die integration.

Key features of CSS-V3 include:

  • High-performance CPU clusters: Optimized for server workloads and data throughput.

  • Advanced memory management: Efficient handling of data across multiple processing cores.

  • Interconnect technology: Enabling high-speed, low-latency communication within the subsystem.

The CSS‑V3 subsystem is fully supported by Arm's Fixed Virtual Platform, enabling pre-silicon testing of these capabilities.

RD‑V3 Platform Introduction

The RD‑V3 platform is a comprehensive reference design built around Arm’s Neoverse V3 CPUs, along with Cortex-M55 and Cortex-M7 microcontrollers. This platform enables efficient high-performance computing and robust platform management:

Component Description
Neoverse V3 The primary application processor responsible for executing OS and payloads
Cortex M7 Implements the System Control Processor (SCP) for power, clocks, and init
Cortex M55 Hosts the Runtime Security Engine (RSE), providing secure boot and runtime integrity

These subsystems work together in a coordinated architecture, communicating through shared memory regions, control buses, and platform protocols. This enables multi-stage boot processes and robust secure boot implementations.

Here is the Neoverse Reference Design Platform Software Stack for your reference.

img1 alt-text#center

Develop and Validate Without Hardware

In traditional development workflows, system validation cannot begin until silicon is available—often introducing risk and delay.

To address this, Arm provides the Fixed Virtual Platform (FVP) —a complete simulations model that emulates full Arm SoC behavior on a host machine. The CSS‑V3 platform is available in multiple FVP configurations, allowing developers to select the model that best fits their specific development and validation needs.

Key Capabilities of FVP:

  • Multi-core CPU simulation with SMP boot
  • Multiple UART interfaces for serial debug and monitoring
  • Compatible with TF‑A, UEFI, GRUB, and Linux kernel images
  • Provides boot logs, trace outputs, and interrupt event visibility for debugging

FVP enables developers to verify boot sequences, debug firmware handoffs, and even simulate RSE behaviors—all before first silicon.

Comparing different version of RD-V3 FVP

To support different use cases and levels of platform complexity, Arm offers three virtual models based on the CSS‑v3 architecture: RD‑V3, RD-V3-Cfg1, and RD‑V3‑R1. While they share a common foundation, they differ in chip count, system topology, and simulation flexibility.

Model Description Recommended Use Cases
RD‑V3 Standard single-die platform with full processor and security blocks Ideal for newcomers, firmware bring-up, and basic validation
RD‑V3‑R1 Dual-die platform simulating chiplet-based architecture Suitable for multi-node, interconnect, and advanced boot tests
CFG1 Lightweight model with reduced control complexity for fast startup Best for CI pipelines, unit testing, and quick validations

This Learning Path begins with RD‑V3 as the primary platform for foundational exercises, guiding you through the process of building the software stack and simulating it on FVP to verify the boot sequence. In later modules, you’ll transition to RD‑V3‑R1 to more advanced system simulation, multi-node bring-up, and firmware coordination across components like MCP and SCP.