Enhance image descriptions in documentation for AXI4 peripheral creation and bitstream generation for improved clarity and context.

Author: madeline-underwood

content/learning-paths/embedded-and-microcontrollers/advanced_soc/creating_peripheral.md

@@ -93,7 +93,7 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
 
 12. Save the changes in the file (Ctrl+S). Next, go to the “Package IP – AUP_advanced_SoC” tab, choose the “Customization Parameters” option on the left and click “Merge Changes from Customization Parameters Wizard” to update the IP package with the changes made in HDL files:
 
-    ![. Saving all the changes](images/picture12.png) 
+    ![Screenshot of Vivado Package IP window showing the Customization Parameters page with the Merge changes from Customization Parameters Wizard link highlighted to synchronize HDL code changes with IP packaging](images/picture12.png) 
 
     *Figure 2.6. Saving all the changes*
 

content/learning-paths/embedded-and-microcontrollers/advanced_soc/generating_bitstream.md

@@ -48,7 +48,7 @@ In this section you will generate the bitstream for this project and write a C p
 
 7. Select the “Create a new platform from hardware (XSA)” tab and click browse to select the XSA file you saved earlier:
 
-    ![Adding the XSA file](images/picture29.png) 
+    ![Screenshot of Vitis New Application Project wizard showing the Create a new platform from hardware (XSA) option with a browse button to select the exported hardware description file containing the FPGA design and processor configuration](images/picture29.png) 
 
     *Figure 3.7. Adding the XSA file*