updates

Author: madeline-underwood

content/learning-paths/servers-and-cloud-computing/false-sharing-arm-spe/_index.md

@@ -1,16 +1,15 @@
 ---
 title: Analyze cache behavior with Perf C2C on Arm
 
-draft: true
-cascade:
-    draft: true
+
+
 
 minutes_to_complete: 15
 
-who_is_this_for: This topic is for developers who want to optimize cache access patterns on Arm servers using Perf C2C. 
+who_is_this_for: This topic is for performance-oriented developers working on Arm-based cloud or server systems who want to optimize memory access patterns and investigate cache inefficiencies using Perf C2C and Arm SPE.
 
 learning_objectives: 
-    - Avoid false sharing in C++ using memory alignment.
+    - Identify and fix false sharing issues using Perf C2C, a cache line analysis tool.
     - Enable and use the Arm Statistical Profiling Extension (SPE) on Linux systems.
     - Investigate cache line performance with Perf C2C.
 

content/learning-paths/servers-and-cloud-computing/false-sharing-arm-spe/how-to-1.md

@@ -5,32 +5,35 @@ weight: 2
 ### FIXED, DO NOT MODIFY
 layout: learningpathall
 ---
-
 ## Introduction to the Arm Statistical Profiling Extension (SPE)
 
-Standard performance tracing relies on counting completed instructions, capturing only architectural instructions without revealing the actual memory addresses, pipeline latencies, or considering micro-operations in flight. Moreover, the “skid” phenomenon where events are falsely attributed to later instructions can mislead developers. 
+Traditional Linux performance profiling tools often rely on retired instruction counts, which lack visibility into memory addresses, cache latencies, and micro-operation behavior. Moreover, the “skid” phenomenon where events are falsely attributed to later instructions can mislead developers. 
 
 SPE integrates sampling directly into the CPU pipeline, triggering on individual micro-operations rather than retired instructions, thereby eliminating skid and blind spots. Each SPE sample record includes relevant metadata, such as data addresses, per-µop pipeline latency, triggered PMU event masks, and the memory hierarchy source, enabling fine-grained and precise cache analysis. 
 
-This enables software developers to tune user-space software for characteristics such as memory latency and cache accesses. Importantly, cache statistics are enabled with the Linux Perf cache-to-cache (C2C) utility.
+SPE helps developers optimize user-space applications by showing where cache latency or memory access delays are happening. Importantly, cache statistics are enabled with the Linux Perf cache-to-cache (C2C) utility.
 
-Please refer to the [Arm SPE white paper](https://developer.arm.com/documentation/109429/latest/) for more details. 
+To learn more, check out the [Arm SPE white paper](https://developer.arm.com/documentation/109429/latest/) for more information. 
 
 In this Learning Path, you will use SPE and Perf C2C to diagnose a cache issue for an application running on a Neoverse server.
 
-## False sharing within the cache
+## What is false sharing and why should I care about it?
+
+In large-scale, multithreaded applications, false sharing can degrade performance by introducing hundreds of unnecessary cache line invalidations per second - often with no visible red flags in the source code.
+
+Even when two threads touch entirely separate variables, modern processors move data in fixed-size cache lines (nominally 64-bytes). If those distinct variables happen to occupy bytes within the same line, every time one thread writes its variable the core’s cache must gain exclusive ownership of the whole line, forcing the other core’s copy to be invalidated. 
 
-Even when two threads touch entirely separate variables, modern processors move data in fixed-size cache lines (nominally 64-bytes). If those distinct variables happen to occupy bytes within the same line, every time one thread writes its variable the core’s cache must gain exclusive ownership of the whole line, forcing the other core’s copy to be invalidated. The second thread, still working on its own variable, then triggers a coherence miss to fetch the line back, and the ping-pong pattern repeats. Please see the illustration below, taken from the Arm SPE white paper, for a visual explanation.
+The second thread, still working on its own variable, then triggers a coherence miss to fetch the line back, and the ping-pong pattern repeats. See the illustration below, taken from the Arm SPE white paper, for a visual explanation.
 
-![false_sharing_diagram](./false_sharing_diagram.png)
+![false_sharing_diagram alt-text#center](./false_sharing_diagram.png "Two threads on separate cores alternately gain exclusive access to the same cache line.")
 
 Because false sharing hides behind ordinary writes, the easiest time to eliminate it is while reading or refactoring the source code by padding or realigning the offending variables before compilation. In large, highly concurrent codebases, however, data structures are often accessed through several layers of abstraction, and many threads touch memory via indirection, so the subtle cache-line overlap may not surface until profiling or performance counters reveal unexpected coherence misses.
 
 From a source-code perspective nothing is “shared,” but at the hardware level both variables are implicitly coupled by their physical location.
 
 ## Alignment to cache lines
 
-In C++11, you can manually specify the alignment of an object with the `alignas` specifier. For example, the C++11 source code below manually aligns the the `struct` every 64 bytes (typical cache line size on a modern processor). This ensures that each instance of `AlignedType` is on a separate cache line. 
+In C++11, you can manually specify the alignment of an object with the `alignas` specifier. For example, the C++11 source code below manually aligns the `struct` every 64 bytes (typical cache line size on a modern processor). This ensures that each instance of `AlignedType` is on a separate cache line. 
 
 ```cpp
 #include <atomic>
@@ -43,7 +46,7 @@ struct alignas(64) AlignedType {
 
 
 int main() {
-  // If we create four atomic integers like this, there's a high probability
+  // If you create four atomic integers like this, there's a high probability
   // they'll wind up next to each other in memory
   std::atomic<int> a;
   std::atomic<int> b;
@@ -74,9 +77,9 @@ int main() {
 }
 ```
 
-The example output below shows the variables e, f, g and h occur at least 64-bytes apart in the byte-addressable architecture. Whereas variables a, b, c and d occur 8 bytes apart, occupying the same cache line. 
+The example output below shows the variables e, f, g and h occur at least 64 bytes apart in the byte-addressable architecture. Whereas variables a, b, c, and d occur 8 bytes apart, occupying the same cache line. 
 
-Although this is a contrived example, in a production workload there may be several layers of indirection that unintentionally result in false sharing. For these complex cases, to understand the root cause you will use Perf C2C.
+Although this is a contrived example, in a production workload there might be several layers of indirection that unintentionally result in false sharing. For these complex cases, to understand the root cause you will use Perf C2C.
 
 ```output
 Without Alignment can occupy same cache line
@@ -96,4 +99,9 @@ Address of AlignedType g - 0xffffeb6c60c0
 Address of AlignedType h - 0xffffeb6c6080
 ```
 
-Continue to the next section to learn how to set up a system to run Perf C2C.
+## Summary
+
+In this section, you learned what Arm SPE is and why it’s a game-changer for performance profiling. You also saw how a subtle issue like false sharing can slow down multithreaded code — and how to avoid it using alignment in C++.
+
+Next up: you’ll set up your environment and get ready to run Perf C2C on a real application. 
+

content/learning-paths/servers-and-cloud-computing/false-sharing-arm-spe/how-to-2.md

@@ -23,7 +23,7 @@ uname -r
 
 The output includes the CPU type and kernel release version:
 
-```ouput
+```output
 Model name:                           Neoverse-N1
 6.1.134-152.225.amzn2023.aarch64
 ```
@@ -43,7 +43,7 @@ Run the following command to confirm if the SPE kernel module is loaded:
 sudo modprobe arm_spe_pmu
 ```
 
-If the module is not loaded (blank output), SPE may still be available.
+If the module is not loaded (blank output), SPE might still be available.
 
 Run this command to check if SPE is included in the kernel:
 
@@ -63,11 +63,11 @@ If the output is blank then SPE is not available.
 
 You can install and run a Python script named Sysreport to summarize your system's performance profiling capabilities.
 
-Refer to [Get ready for performance analysis with Sysreport](https://learn.arm.com/learning-paths/servers-and-cloud-computing/sysreport/) to learn how to install and run it.
+See [Get ready for performance analysis with Sysreport](https://learn.arm.com/learning-paths/servers-and-cloud-computing/sysreport/) to learn how to install and run it.
 
 Look at the Sysreport output and confirm SPE is available by checking the `perf sampling` field. 
 
-If the printed value is SPE then SPE is available.
+If the printed value is SPE, then SPE is available.
 
 ```output
 ...
@@ -105,9 +105,9 @@ Assign capabilities to Perf by running:
 sudo setcap cap_perfmon,cap_sys_ptrace,cap_sys_admin+ep $(which perf)
 ```
 
-If `arm_spe` is not available because of your system configuration or if you don't have PMU permission, the `perf c2c` command will fail. 
+If `arm_spe` is not available because of your system configuration or if you don't have PMU permission, the `perf c2c` command fails. 
 
-To confirm Perf can access SPE run:
+To confirm Perf can access SPE, run:
 
 ```bash
 perf c2c record
@@ -120,7 +120,7 @@ failed: memory events not supported
 ```
 
 {{% notice Note %}}
-If you are unable to use SPE it may be a restriction based on your cloud instance size or operating system.
+If you are unable to use SPE it might be a restriction based on your cloud instance size or operating system.
 
 Generally, access to a full server (also known as metal instances) with a relatively new kernel is needed for Arm SPE support.