reviewing memory subsystem with ASCT

Author: jasonrandrews

content/learning-paths/servers-and-cloud-computing/memory-subsystem/cache-hierarchy.md

@@ -14,7 +14,7 @@ Each memory access is satisfied by the closest level of the hierarchy that conta
 
 Both systems use 4-way L1 caches with 64-byte lines and 8-way L2 caches, also with 64-byte lines. The key architectural differences are in L2 size and whether a shared last-level cache is present.
 
-Graviton2 (Neoverse N1) has a 1 MB private L2 per core and a 32 MB shared L3 across all 64 cores. Graviton4 (Neoverse V2) doubles the L2 to 2 MB and has a 36 MB shared L3. The larger L2 on V2 reduces traffic to the shared L3 and lowers contention in multi-threaded workloads, which is especially beneficial for workloads with per-thread working sets between 1 MB and 2 MB.
+Graviton2 (Neoverse N1) has a 1 MB private L2 per core and a 32 MB shared L3 across all 64 cores. Graviton4 (Neoverse V2) doubles the L2 to 2 MB and has a 36 MB shared L3. The larger L2 on Neoverse V2 reduces traffic to the shared L3 and lowers contention in multi-threaded workloads, which is especially beneficial for workloads with per-thread working sets between 1 MB and 2 MB.
 
 Some SoCs add a System Level Cache (SLC) beyond L3, sitting between the CPU cluster and the memory controllers and serving both CPU and GPU traffic.
 

content/learning-paths/servers-and-cloud-computing/memory-subsystem/comparative-analysis.md

@@ -152,8 +152,8 @@ Collect the key measurements from each system into a comparison table:
 The latency measurements from `latency-sweep` reveal how each generation's cache hierarchy performs:
 
 - **L1 latency** is similar across both generations (1.6 ns vs 1.4 ns). L1 caches are designed for very low latency (typically a few cycles), so the small difference reflects clock speed rather than cache microarchitecture.
-- **L2 latency** improves by 27% on Graviton4 (4.0 ns vs 5.4 ns). Neoverse V2 has a 2 MB private L2 compared to N1's 1 MB. Despite the larger size, V2's improved cache pipeline delivers lower latency.
-- **LLC latency** improves by 24% on Graviton4 (21.8 ns vs 28.8 ns), despite the L3 being only slightly larger (36 MB vs 32 MB). This reflects microarchitectural improvements in the V2 cache interconnect.
+- **L2 latency** improves by 27% on Graviton4 (4.0 ns vs 5.4 ns). Neoverse V2 has a 2 MB private L2 compared to Neoverse N1's 1 MB. Despite the larger size, Neoverse V2's improved cache pipeline delivers lower latency.
+- **LLC latency** improves by 24% on Graviton4 (21.8 ns vs 28.8 ns), despite the L3 being only slightly larger (36 MB vs 32 MB). This reflects microarchitectural improvements in the Neoverse V2 cache interconnect.
 - **DRAM latency** is higher on Graviton4 (114.6 ns vs 95.5 ns, +20%). DDR5 trades slightly higher access latency for significantly more bandwidth per channel compared to DDR4.
 
 ### Loaded latency
@@ -170,9 +170,9 @@ The `loaded-latency` results reveal the latency-bandwidth tradeoff:
 Single-core bandwidth from `bandwidth-sweep` shows the throughput capacity at each cache level:
 
 - **L1 bandwidth** doubles on Graviton4 (321 vs 159 GB/s, +101%). This likely reflects a combination of higher clock speed and microarchitectural throughput improvements in Neoverse V2.
-- **L2 bandwidth** improves by 29% on Graviton4 (95 vs 73 GB/s), due to the wider L2 fill path and microarchitectural improvements in V2.
+- **L2 bandwidth** improves by 29% on Graviton4 (95 vs 73 GB/s), due to the wider L2 fill path and microarchitectural improvements in Neoverse V2.
 - **LLC bandwidth** more than doubles on Graviton4 (80 vs 36 GB/s, +123%), reflecting improvements in the interconnect and shared cache design.
-- **DRAM bandwidth (single core)** improves by 77% on Graviton4 (37 vs 21 GB/s). V2 supports more outstanding memory requests than N1, and DDR5 provides more bandwidth per channel than DDR4.
+- **DRAM bandwidth (single core)** improves by 77% on Graviton4 (37 vs 21 GB/s). Neoverse V2 supports more outstanding memory requests than Neoverse N1, and DDR5 provides more bandwidth per channel than DDR4.
 
 Peak bandwidth from `peak-bandwidth` shows the system-level memory controller capacity:
 

content/learning-paths/servers-and-cloud-computing/memory-subsystem/streaming-bandwidth.md

@@ -59,9 +59,9 @@ The `bandwidth-sweep` benchmark reports the bandwidth at the optimal data size f
 Key differences to look for between Graviton2 and Graviton4:
 
 - **L1 bandwidth**: Graviton4 shows roughly 2x the L1 bandwidth of Graviton2. This likely reflects a combination of higher clock speed and microarchitectural throughput improvements in Neoverse V2.
-- **L2 bandwidth**: V2's larger 2 MB L2 keeps more data in the fast private cache, and microarchitectural improvements on V2 also increase L2 fill bandwidth.
-- **LLC bandwidth**: Graviton4 more than doubles the LLC bandwidth of Graviton2, reflecting improvements in the interconnect and shared cache design on V2.
-- **DRAM bandwidth (single core)**: Graviton4 achieves higher single-core DRAM throughput because V2 supports more outstanding memory requests than N1, and DDR5 provides more bandwidth per channel than DDR4.
+- **L2 bandwidth**: Neoverse V2's larger 2 MB L2 keeps more data in the fast private cache, and microarchitectural improvements on Neoverse V2 also increase L2 fill bandwidth.
+- **LLC bandwidth**: Graviton4 more than doubles the LLC bandwidth of Graviton2, reflecting improvements in the interconnect and shared cache design on Neoverse V2.
+- **DRAM bandwidth (single core)**: Graviton4 achieves higher single-core DRAM throughput because Neoverse V2 supports more outstanding memory requests than Neoverse N1, and DDR5 provides more bandwidth per channel than DDR4.
 
 ### Bytes per cycle
 

content/learning-paths/servers-and-cloud-computing/memory-subsystem/system-overview.md

@@ -136,7 +136,7 @@ NUMA:
 
 The two systems span two generations of Arm Neoverse server cores. Graviton2 uses Neoverse N1 cores with private 1 MB L2 caches per core and a 32 MB shared L3. Graviton4 uses Neoverse V2 cores with 2 MB private L2 caches per core and a 36 MB shared L3. These differences in cache sizes and memory technology directly impact the memory latency, bandwidth, and scaling behavior you observe in later benchmarks.
 
-Notice that the Neoverse V2 `Flags` field is significantly longer than Neoverse N1. This reflects the newer Arm architecture: V2 is based on Armv9, which adds extensions like SVE2, BF16, and I8MM that are absent on the Armv8-based N1.
+Notice that the Neoverse V2 `Flags` field is significantly longer than Neoverse N1. This reflects the newer Arm architecture: Neoverse V2 is based on Armv9, which adds extensions like SVE2, BF16, and I8MM that are absent on the Armv8-based Neoverse N1.
 
 ## Check DRAM configuration