Update .md references for renamed images

Author: annietllnd

content/install-guides/mcuxpresso_vs.md

@@ -65,7 +65,7 @@ Download and run the installer.
 
 Select one or more packages and click `Install`. 
 
-![MCUXpresso Installer #center](/install-guides/_images/MCUXpresso_Installer.png)
+![MCUXpresso Installer #center](/install-guides/_images/mcuxpresso_installer.png)
 
 ### Are there other embedded development extensions for VS Code?
 

content/install-guides/openvscode-server.md

@@ -105,7 +105,7 @@ With the port open, substitute the public IP address of the instance instead of
 
 On ChromeOS you can use the Linux configuration settings to automatically do port forwarding. No SSH connection is needed.
 
-![port forwarding #center](/install-guides/_images/ChromeOSpf.png)
+![port forwarding #center](/install-guides/_images/chromeospf.png)
 
 ## What other configuration options are available?
 

…eidiai-explainer/KleidiAI-src-matmul.JPG …eidiai-explainer/kleidiai-src-matmul.JPGcontent/learning-paths/cross-platform/kleidiai-explainer/KleidiAI-src-matmul.JPG renamed to content/learning-paths/cross-platform/kleidiai-explainer/kleidiai-src-matmul.JPG content/learning-paths/cross-platform/kleidiai-explainer/KleidiAI-src-matmul.JPG renamed to content/learning-paths/cross-platform/kleidiai-explainer/kleidiai-src-matmul.JPG

@@ -16,7 +16,7 @@ There are essentially two types of KleidiAI micro-kernels today:
 2. Matrix Multiplication routines - the three directories with the prefix `matmul_clamp`. Each directory contains routines specialized for a specific input data type.
 
 
-![KleidiAI stuff](KleidiAI-src.JPG "KleidiAI src directory")
+![KleidiAI stuff](kleidiai-src.JPG "KleidiAI src directory")
 
 ### What are the quantization levels that KleidiAI supports?
 KleidiAI has multiple matrix multiplication micro-kernels, and dynamic quantization routines, to optimally support all model quantization levels. To learn more about model quantization and how selecting the right quantization level affects your AI-based application, refer to [this Learning Path](/learning-paths/servers-and-cloud-computing/llama-cpu/llama-chatbot#quantization-format).

…form/kleidiai-explainer/KleidiAI-src.JPG …form/kleidiai-explainer/kleidiai-src.JPGcontent/learning-paths/cross-platform/kleidiai-explainer/KleidiAI-src.JPG renamed to content/learning-paths/cross-platform/kleidiai-explainer/kleidiai-src.JPG content/learning-paths/cross-platform/kleidiai-explainer/KleidiAI-src.JPG renamed to content/learning-paths/cross-platform/kleidiai-explainer/kleidiai-src.JPG

@@ -299,7 +299,7 @@ Then select the **Reopen in Container** menu entry as shown below.
 
 It automatically finds and uses `.devcontainer/devcontainer.json`:
 
-![VSCode Docker alt-text#center](VSCode.png "Figure 1: Setting up the Docker container.")
+![VSCode Docker alt-text#center](vscode.png "Figure 1: Setting up the Docker container.")
 
 All your commands now run within the container, so there is no need to prepend
 them with a Docker invocation, as VS Code handles all this seamlessly for you.

content/learning-paths/cross-platform/kleidiai-explainer/page2.md

@@ -18,7 +18,7 @@ The advantages are:
 
 Peer to Peer connections are created by installing a software package with initiator support on the initiator device. Install the Remote.It Desktop application or Remote.It CLI on your initiator device to support Peer to Peer connection.
 
-![example image alt-text#center](Remote.It-Connections.png "Proxy and Peer to Peer Connection Illustration")
+![example image alt-text#center](remote.it-connections.png "Proxy and Peer to Peer Connection Illustration")
 
 ## Peer to Peer Connections
 

content/learning-paths/cross-platform/multiplying-matrices-with-sme2/1-get-started.md

@@ -12,23 +12,23 @@ Follow the steps outline below to connect the AXI4 peripheral you created in the
 
 1. Right-click on the empty space again in the diagram and choose “Create Port...” (Ctrl+K). Create 2 ports with the following settings and names: 
 
-    ![Creating output port](images/Picture15.png) 
+    ![Creating output port](images/picture15.png) 
 
     *Figure 3.1. Creating output port*
 
-    ![Creating input port](images/Picture16.png) 
+    ![Creating input port](images/picture16.png) 
 
     *Figure 3.2. Creating input port*
 
 2. Wire the “sw[3:0]” input to the “sw[3:0]” port of the “axi_gpio_asoc_0” block and the same for the “led[3:0]” output to the equivalent port of the block as shown in the diagram below. This connects them to external ports of the ZYNQ chip:
 
-    ![Vivado block diagram](images/Picture17.png) 
+    ![Vivado block diagram](images/picture17.png) 
 
     *Figure 3.3. Vivado block diagram*
 
 3. Two IP blocks will be generated automatically. The “Processor System Reset” IP is used to generate reset signals for different peripherals. The “AXI Interconnect” IP here is used to interconnect AXI4-Lite Subordinate and AXI Manager. Select the “Address Editor” tab next to “Diagram” and change the “64K” to “4K”. Save all your progress.
 
-    ![Changing peripheral address settings](images/Picture18.png) 
+    ![Changing peripheral address settings](images/picture18.png) 
 
     *Figure 3.4. Changing peripheral address settings*
 
@@ -40,26 +40,26 @@ Follow the steps outline below to connect the AXI4 peripheral you created in the
 
 5. Right-click the “Generate Bitstream” option in the “Flow Navigator” on the left and select “Bitstream settings”. Click the three dots next to “tcl.pre”:
 
-    ![Changing bitstream settings](images/Picture19.png) 
+    ![Changing bitstream settings](images/picture19.png) 
 
     *Figure 3.5. Changing bitstream settings*
 
 6. Select the “New Script” option, click the three dots next to the empty box, choose the “pins.tcl” file you created earlier and click “Ok” on all windows.
 Right-click the “Constraints” under the sources tab and select “Add sources”:
 
-    ![Adding sources](images/Picture20.png) 
+    ![Adding sources](images/picture20.png) 
 
     *Figure 3.6. Adding sources*
 
 7. Select “Add or create constraints” and click “Next”. Select “Create File”, give any name to the file for example pin_constraints, and click “Finish”:
 
-    ![Creating a constraints file](images/Picture21.png) 
+    ![Creating a constraints file](images/picture21.png) 
 
     *Figure 3.7. Creating a constraints file*
 
 8. Expand the “Constraints” folder within the “Sources” tab and double-click the file you just created to open it. Add the following constraints from [Digilent/Zybo-Z7-10-Pmod-VGA/blob/master/src/constraints/Zybo-Z7-Master.xdc](https://github.com/Digilent/Zybo-Z7-10-Pmod-VGA/blob/master/src/constraints/Zybo-Z7-Master.xdc), and save the file: 
 
-    ![Editing constraints file](images/Picture22.png) 
+    ![Editing constraints file](images/picture22.png) 
 
     *Figure 3.8. Editing constraints file*
 

content/learning-paths/cross-platform/remoteit/connections.md

@@ -12,19 +12,19 @@ The Xilinx Vivado tools provide a simplified way to create an AXI4 peripheral. Y
 
 1. Start by clicking “Tools” -> “Create and Package New IP”. Click “Next” and choose the following option:
 
-    ![Creating AXI4 peripheral](images/Picture7.png) 
+    ![Creating AXI4 peripheral](images/picture7.png) 
 
     *Figure 2.1. Creating AXI4 peripheral*
 
 2. Give the following name to the IP (you may keep the IP location path as provided by default):
 
-    ![Adding peripheral details](images/Picture8.jpg) 
+    ![Adding peripheral details](images/picture8.jpg) 
 
     *Figure 2.2. Adding peripheral details*
 
 3. You need a Subordinate interface and four 32-bit registers for the switches and LEDs.
 
-    ![Peripheral settings for Subordinate interface](images/Picture9.png) 
+    ![Peripheral settings for Subordinate interface](images/picture9.png) 
 
     *Figure 2.3. Peripheral settings for Subordinate interface*
 
@@ -36,7 +36,7 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
 
 5. Double-click to open the top-level Verilog file called “AUP_advanced_SoC_v1_0.v”:
 
-    ![Editing top-level Verilog file](images/Picture10.png) 
+    ![Editing top-level Verilog file](images/picture10.png) 
 
     *Figure 2.4. Editing top-level Verilog file*
 
@@ -64,7 +64,7 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
     ```
 8. Save the changes in the file (Ctrl+S). Next, expand and open the other Verilog file (AUP_advanced_SoC_v1_0_S00_AXI.v) shown below:
 
-    ![Edit the second Verilog file](images/Picture11.png) 
+    ![Edit the second Verilog file](images/picture11.png) 
 
     *Figure 2.5. Edit the second Verilog file*
 
@@ -93,7 +93,7 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
 
 12. Save the changes in the file (Ctrl+S). Next, go to the “Package IP – AUP_advanced_SoC” tab, choose the “Customization Parameters” option on the left and click “Merge Changes from Customization Parameters Wizard” to update the IP package with the changes made in HDL files:
 
-    ![. Saving all the changes](images/Picture12.png) 
+    ![. Saving all the changes](images/picture12.png) 
 
     *Figure 2.6. Saving all the changes*
 
@@ -127,15 +127,15 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
     ```
 15. Then, click on “Settings” (under “Project Manager”) in the “Flow Navigator” menu on the left. Expand the “IP” section in the new window that appears and choose the “Repository” option. 
 
-    ![Adding IP Repository](images/Picture13.png) 
+    ![Adding IP Repository](images/picture13.png) 
 
     *Figure 2.7. Adding IP Repository*
 
 16. Click the “+” option under “IP Repositories” on the right and choose the AXI4 peripheral folder you created earlier (if it hasn’t already appeared) and click “Ok”. Right-click in the empty space of the “Diagram” box again and choose “Add IP”. Type “custom” in the search box and choose “custom_axi_gpio_asoc_v1_0” from the options. 
 
 17. Click “Run Connection Automation” and then click “OK” to connect the AXI-Lite Subordinate interface on GPIO peripheral to the AXI Manager interface on Arm processor.
 
-    ![Connect AXI-Lite Subordinate interface (Custom IP) to AXI Manager interface](images/Picture14.png) 
+    ![Connect AXI-Lite Subordinate interface (Custom IP) to AXI Manager interface](images/picture14.png) 
 
     *Figure 2.8. Connect AXI-Lite Subordinate interface (Custom IP) to AXI Manager interface*
 

content/learning-paths/embedded-and-microcontrollers/advanced_soc/connecting_peripheral.md

@@ -12,56 +12,56 @@ In this section you will generate the bitstream for this project and write a C p
 
 1. Under the “Sources” tab on the left, expand the “Design Sources” folder, right-click the design1.bd file, choose the “Create HDL Wrapper” and select all default options. 
 
-    ![Creating HDL Wrapper](images/Picture23.png) 
+    ![Creating HDL Wrapper](images/picture23.png) 
 
     *Figure 3.1. Creating HDL Wrapper*
 
 2. Save any other changes and click “Generate Bitstream” on the left and click “Ok” for all pop-ups. This process takes some time. Once the process is done, select “Open Hardware Manager”:
 
-    ![Generating bitstream and uploading to board](images/Picture24.png) 
+    ![Generating bitstream and uploading to board](images/picture24.png) 
 
     *Figure 3.2. Generating bitstream and uploading to board*
 
 3. Connect the board and make sure the jumper (JP3) above the red LED on the Zybo board is in JTAG mode. Then, in Vivado, click “Auto Connect” in the Hardware Manager as shown below:
 
-    ![Connecting the board](images/Picture25.png) 
+    ![Connecting the board](images/picture25.png) 
 
     *Figure 3.3. Connecting the board*
 
 4. Right-click on the board, select “Program Device” as shown below and click “Program” on the pop-up window. 
 
-    ![Programming the board](images/Picture26.png) 
+    ![Programming the board](images/picture26.png) 
 
     *Figure 3.4. Programming the board*
 
 5. Once the board is programmed, the green LED labeled “LD12” should light up on the board. Click “File” on the main menu bar and select “Export” -> “Export Hardware” and click “Next” on the pop-up window. Choose the following option on the next page:
 
-    ![Exporting hardware and bitstream file](images/Picture27.png) 
+    ![Exporting hardware and bitstream file](images/picture27.png) 
 
     *Figure 3.5. Exporting hardware and bitstream file* 
 
 6. Choose the “export to” location as the project folder and save the file. Then click “Finish”. Next, click “Tools” on the main menu bar and select “Launch Vitis IDE”. Choose the same project folder as your workspace. Click “File” -> “New” -> “Application Project”.
 
-    ![Creating a new application project](images/Picture28.png) 
+    ![Creating a new application project](images/picture28.png) 
 
     *Figure 3.6. Creating a new application project*
 
 7. Select the “Create a new platform from hardware (XSA)” tab and click browse to select the XSA file you saved earlier:
 
-    ![Adding the XSA file](images/Picture29.png) 
+    ![Adding the XSA file](images/picture29.png) 
 
     *Figure 3.7. Adding the XSA file*
 
 8. Click next and give a name (e.g. led_system) to the application project. Click “Next” until you reach the following page and choose “Empty Application(C)” and click “Finish”:
 
-    ![Creating an empty C Application](images/Picture30.png) 
+    ![Creating an empty C Application](images/picture30.png) 
 
     *Figure 3.8. Creating an empty C Application*
 
 
 9. Then right-click the “src” folder within the application project you created and add a new file called “main.c”. 
 
-    ![Adding a main.c file](images/Picture31.png) 
+    ![Adding a main.c file](images/picture31.png) 
 
     *Figure 3.9. Adding a main.c file*
 
@@ -81,7 +81,7 @@ In this section you will generate the bitstream for this project and write a C p
 
 12. Right-click the application project in the explorer tab, select “Build Project” and ensure that the build is successful. Then right click again and select “Run As” and then “1 Launch Hardware” to upload everything to the board.
 
-    ![Running the program on the board.](images/Picture32.png) 
+    ![Running the program on the board.](images/picture32.png) 
 
     *Figure 3.10. Running the program on the board.*