nits

Author: anupras-mohapatra-arm

content/learning-paths/embedded-and-microcontrollers/avh_ppocr/_index.md

@@ -34,9 +34,8 @@ generated_summary_faq:
   summary: >-
     You'll export a PaddlePaddle OCR text recognition inference
     model, compile it with TVMC, and deploy the result to the Arm Corstone-300 Fixed Virtual
-    Platform (FVP) with Cortex-M55 processors using Arm Virtual Hardware. You'll follow an end-to-end
-    flow that starts with a pre-trained PaddlePaddle model, produces a TVMC-compiled output for
-    the target, and runs the workload in a bare-metal environment on the FVP. Along the way, you'll
+    Platform (FVP) with Cortex-M55 processors using Arm Virtual Hardware. Starting with a pre-trained PaddlePaddle model, you'll produce a TVMC-compiled output for
+    the target, and run the workload in a bare-metal environment on the FVP. Along the way, you'll
     make the key export, compilation, and deployment choices required for Cortex-M, then validate
     the workflow by executing the model on the virtual platform.
   faqs:

content/learning-paths/embedded-and-microcontrollers/avh_vio/_index.md

@@ -48,7 +48,7 @@ generated_summary_faq:
   - question: Where is the LED example located after I clone the repository?
     answer: >-
       After cloning, navigate into the `leds_example` directory to work with the sample.
-  - question: I haven’t launched Arm Virtual Hardware yet—what should I do first?
+  - question: I haven’t launched Arm Virtual Hardware yet — what should I do first?
     answer: >-
       Start the Arm Virtual Hardware AMI in an AWS account and follow the Arm Virtual Hardware
       install guide to reach the AVH terminal.

content/learning-paths/embedded-and-microcontrollers/bare-metal/_index.md

@@ -36,7 +36,7 @@ generated_summary_faq:
     it with Arm Compiler for Embedded, and run it on the `FVP_Base_AEMvA` model. After bringing
     up a Hello World example that uses semihosting for `printf`, you'll replace that mechanism by retargeting
     output to the PL011 UART provided by the Fixed Virtual Platform. You'll add a minimal EL3 reset handler
-    to boot only one processor and place the remaining cores into sleep. You'll then
+    to boot only one processor and place the remaining cores into sleep. Then, you'll
     introduce basic exception handling by routing exceptions to EL3 and configuring the Generic
     Interrupt Controller (GICv3) with a timer as an interrupt source, enabling a simple event‑driven
     workflow that you can observe on the model.