Merge pull request #3095 from madeline-underwood/advanced

Advanced

Author: jasonrandrews

content/learning-paths/embedded-and-microcontrollers/advanced_soc/_index.md

@@ -3,6 +3,8 @@ title: Design an AXI-Lite peripheral to control GPIOs
 
 minutes_to_complete: 60
 
+description: Learn how to design and integrate a custom AXI-Lite peripheral with a Cortex-A9 processor on the Zybo Z7-10 board using Vivado, configuring GPIOs to control LEDs based on switch inputs.
+
 who_is_this_for: This is an introductory topic for software developers interested in System on Chip Design.
 
 learning_objectives: 

content/learning-paths/embedded-and-microcontrollers/advanced_soc/connecting_peripheral.md

@@ -12,23 +12,23 @@ Follow the steps outline below to connect the AXI4 peripheral you created in the
 
 1. Right-click on the empty space again in the diagram and choose “Create Port...” (Ctrl+K). Create 2 ports with the following settings and names: 
 
-    ![Creating output port](images/picture15.png) 
+    ![Screenshot of Vivado Create Port dialog showing settings for creating an led output port with Direction set to Output and Type set to Data, width 4 bits to connect to external LEDs on the Zybo board](images/picture15.png) 
 
     *Figure 3.1. Creating output port*
 
-    ![Creating input port](images/picture16.png) 
+    ![Screenshot of Vivado Create Port dialog showing settings for creating an sw input port with Direction set to Input and Type set to Data, width 4 bits to read switch states from the Zybo board](images/picture16.png) 
 
     *Figure 3.2. Creating input port*
 
 2. Wire the “sw[3:0]” input to the “sw[3:0]” port of the “axi_gpio_asoc_0” block and the same for the “led[3:0]” output to the equivalent port of the block as shown in the diagram below. This connects them to external ports of the ZYNQ chip:
 
-    ![Vivado block diagram](images/picture17.png) 
+    ![Screenshot of Vivado block design showing the complete system with ZYNQ Processing System, AXI Interconnect, custom GPIO peripheral, and external sw and led ports wired together for switch input and LED output control](images/picture17.png) 
 
     *Figure 3.3. Vivado block diagram*
 
 3. Two IP blocks will be generated automatically. The “Processor System Reset” IP is used to generate reset signals for different peripherals. The “AXI Interconnect” IP here is used to interconnect AXI4-Lite Subordinate and AXI Manager. Select the “Address Editor” tab next to “Diagram” and change the “64K” to “4K”. Save all your progress.
 
-    ![Changing peripheral address settings](images/picture18.png) 
+    ![Screenshot of Vivado Address Editor tab showing the axi_gpio_asoc_0 peripheral address range field where you change the default 64K allocation to 4K to efficiently use memory address space](images/picture18.png) 
 
     *Figure 3.4. Changing peripheral address settings*
 
@@ -40,26 +40,26 @@ Follow the steps outline below to connect the AXI4 peripheral you created in the
 
 5. Right-click the “Generate Bitstream” option in the “Flow Navigator” on the left and select “Bitstream settings”. Click the three dots next to “tcl.pre”:
 
-    ![Changing bitstream settings](images/picture19.png) 
+    ![Screenshot of Vivado Bitstream Settings dialog showing the tcl.pre field with a browse button where you specify the pins.tcl script to suppress I/O pin warnings during bitstream generation](images/picture19.png) 
 
     *Figure 3.5. Changing bitstream settings*
 
 6. Select the “New Script” option, click the three dots next to the empty box, choose the “pins.tcl” file you created earlier and click “Ok” on all windows.
 Right-click the “Constraints” under the sources tab and select “Add sources”:
 
-    ![Adding sources](images/picture20.png) 
+    ![Screenshot of Vivado Sources panel showing the right-click context menu on Constraints with Add Sources option highlighted to add physical pin constraint files for the FPGA](images/picture20.png) 
 
     *Figure 3.6. Adding sources*
 
 7. Select “Add or create constraints” and click “Next”. Select “Create File”, give any name to the file for example pin_constraints, and click “Finish”:
 
-    ![Creating a constraints file](images/picture21.png) 
+    ![Screenshot of Vivado Add or Create Constraints dialog showing the Create File option where you specify the constraint file name that will map GPIO signals to physical FPGA pins on the Zybo board](images/picture21.png) 
 
     *Figure 3.7. Creating a constraints file*
 
 8. Expand the “Constraints” folder within the “Sources” tab and double-click the file you just created to open it. Add the following constraints from [Digilent/Zybo-Z7-10-Pmod-VGA/blob/master/src/constraints/Zybo-Z7-Master.xdc](https://github.com/Digilent/Zybo-Z7-10-Pmod-VGA/blob/master/src/constraints/Zybo-Z7-Master.xdc), and save the file: 
 
-    ![Editing constraints file](images/picture22.png) 
+    ![Screenshot of Vivado XDC constraints file editor showing the PACKAGE_PIN and IOSTANDARD settings for switch and LED pins, which map the sw and led signals to specific physical pins on the Zybo Z7-10 FPGA](images/picture22.png) 
 
     *Figure 3.8. Editing constraints file*
 

content/learning-paths/embedded-and-microcontrollers/advanced_soc/creating_peripheral.md

@@ -12,19 +12,19 @@ The Xilinx Vivado tools provide a simplified way to create an AXI4 peripheral. Y
 
 1. Start by clicking “Tools” -> “Create and Package New IP”. Click “Next” and choose the following option:
 
-    ![Creating AXI4 peripheral](images/picture7.png) 
+    ![Screenshot of Vivado's Create and Package New IP wizard showing the Create a new AXI4 peripheral option selected, which generates template files for an AXI-compliant custom IP block](images/picture7.png) 
 
     *Figure 2.1. Creating AXI4 peripheral*
 
 2. Give the following name to the IP (you may keep the IP location path as provided by default):
 
-    ![Adding peripheral details](images/picture8.jpg) 
+    ![Screenshot of the peripheral details dialog showing the Name field set to AUP_advanced_SoC and fields for Version, Display name, and Description where you configure the custom IP metadata](images/picture8.jpg) 
 
     *Figure 2.2. Adding peripheral details*
 
 3. You need a Subordinate interface and four 32-bit registers for the switches and LEDs.
 
-    ![Peripheral settings for Subordinate interface](images/picture9.png) 
+    ![Screenshot of the Add Interfaces wizard showing the Subordinate interface type selected with Number of Registers set to 4 and Data Width set to 32, configuring the AXI-Lite register bank for GPIO control](images/picture9.png) 
 
     *Figure 2.3. Peripheral settings for Subordinate interface*
 
@@ -36,7 +36,7 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
 
 5. Double-click to open the top-level Verilog file called “AUP_advanced_SoC_v1_0.v”:
 
-    ![Editing top-level Verilog file](images/picture10.png) 
+    ![Screenshot of Vivado Sources panel showing the Design Sources hierarchy with AUP_advanced_SoC_v1_0.v file highlighted, which is the top-level module that needs custom GPIO port declarations added](images/picture10.png) 
 
     *Figure 2.4. Editing top-level Verilog file*
 
@@ -64,7 +64,7 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
     ```
 8. Save the changes in the file (Ctrl+S). Next, expand and open the other Verilog file (AUP_advanced_SoC_v1_0_S00_AXI.v) shown below:
 
-    ![Edit the second Verilog file](images/picture11.png) 
+    ![Screenshot of Vivado Sources panel showing the AUP_advanced_SoC_v1_0_S00_AXI.v file which implements the AXI-Lite slave interface logic and needs modifications for GPIO register mapping](images/picture11.png) 
 
     *Figure 2.5. Edit the second Verilog file*
 
@@ -93,7 +93,7 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
 
 12. Save the changes in the file (Ctrl+S). Next, go to the “Package IP – AUP_advanced_SoC” tab, choose the “Customization Parameters” option on the left and click “Merge Changes from Customization Parameters Wizard” to update the IP package with the changes made in HDL files:
 
-    ![. Saving all the changes](images/picture12.png) 
+    ![Screenshot of Vivado Package IP window showing the Customization Parameters page with the Merge changes from Customization Parameters Wizard link highlighted to synchronize HDL code changes with IP packaging](images/picture12.png) 
 
     *Figure 2.6. Saving all the changes*
 
@@ -127,15 +127,15 @@ These are the basic template files generated for an AXI-Lite peripheral. You can
     ```
 15. Then, click on “Settings” (under “Project Manager”) in the “Flow Navigator” menu on the left. Expand the “IP” section in the new window that appears and choose the “Repository” option. 
 
-    ![Adding IP Repository](images/picture13.png) 
+    ![Screenshot of Vivado Project Settings showing the IP section expanded with Repository selected, where you add the custom IP location so Vivado can find and use the AXI peripheral you created](images/picture13.png) 
 
     *Figure 2.7. Adding IP Repository*
 
 16. Click the “+” option under “IP Repositories” on the right and choose the AXI4 peripheral folder you created earlier (if it hasn’t already appeared) and click “Ok”. Right-click in the empty space of the “Diagram” box again and choose “Add IP”. Type “custom” in the search box and choose “custom_axi_gpio_asoc_v1_0” from the options. 
 
 17. Click “Run Connection Automation” and then click “OK” to connect the AXI-Lite Subordinate interface on GPIO peripheral to the AXI Manager interface on Arm processor.
 
-    ![Connect AXI-Lite Subordinate interface (Custom IP) to AXI Manager interface](images/picture14.png) 
+    ![Screenshot of Vivado block diagram showing the Run Connection Automation dialog with the S_AXI interface of the custom GPIO peripheral ready to be automatically connected to the Zynq processing system's M_AXI_GP0 master port](images/picture14.png) 
 
     *Figure 2.8. Connect AXI-Lite Subordinate interface (Custom IP) to AXI Manager interface*
 

content/learning-paths/embedded-and-microcontrollers/advanced_soc/generating_bitstream.md

@@ -12,43 +12,43 @@ In this section you will generate the bitstream for this project and write a C p
 
 1. Under the “Sources” tab on the left, expand the “Design Sources” folder, right-click the design1.bd file, choose the “Create HDL Wrapper” and select all default options. 
 
-    ![Creating HDL Wrapper](images/picture23.png) 
+    ![Screenshot of Vivado Sources panel showing the right-click context menu on design1.bd with Create HDL Wrapper option highlighted, which generates the top-level Verilog wrapper needed for synthesis](images/picture23.png) 
 
     *Figure 3.1. Creating HDL Wrapper*
 
 2. Save any other changes and click “Generate Bitstream” on the left and click “Ok” for all pop-ups. This process takes some time. Once the process is done, select “Open Hardware Manager”:
 
-    ![Generating bitstream and uploading to board](images/picture24.png) 
+    ![Screenshot of Vivado Bitstream Generation Completed dialog showing the Open Hardware Manager option selected, which you use to program the FPGA with the generated bitstream file](images/picture24.png) 
 
     *Figure 3.2. Generating bitstream and uploading to board*
 
 3. Connect the board and make sure the jumper (JP3) above the red LED on the Zybo board is in JTAG mode. Then, in Vivado, click “Auto Connect” in the Hardware Manager as shown below:
 
-    ![Connecting the board](images/picture25.png) 
+    ![Screenshot of Vivado Hardware Manager showing the Auto Connect button which detects and connects to the Zybo board via JTAG for programming](images/picture25.png) 
 
     *Figure 3.3. Connecting the board*
 
 4. Right-click on the board, select “Program Device” as shown below and click “Program” on the pop-up window. 
 
-    ![Programming the board](images/picture26.png) 
+    ![Screenshot of Vivado Hardware Manager showing the right-click context menu on the detected FPGA device with Program Device option highlighted to upload the bitstream to the Zybo board](images/picture26.png) 
 
     *Figure 3.4. Programming the board*
 
 5. Once the board is programmed, the green LED labeled “LD12” should light up on the board. Click “File” on the main menu bar and select “Export” -> “Export Hardware” and click “Next” on the pop-up window. Choose the following option on the next page:
 
-    ![Exporting hardware and bitstream file](images/picture27.png) 
+    ![Screenshot of Vivado Export Hardware dialog showing the Include bitstream option selected, which packages the hardware design and bitstream into an XSA file for use in Vitis IDE software development](images/picture27.png) 
 
     *Figure 3.5. Exporting hardware and bitstream file* 
 
 6. Choose the “export to” location as the project folder and save the file. Then click “Finish”. Next, click “Tools” on the main menu bar and select “Launch Vitis IDE”. Choose the same project folder as your workspace. Click “File” -> “New” -> “Application Project”.
 
-    ![Creating a new application project](images/picture28.png) 
+    ![Screenshot of Vitis IDE showing the File menu with New > Application Project option selected to create a new embedded software project for the Cortex-A9 processor](images/picture28.png) 
 
     *Figure 3.6. Creating a new application project*
 
 7. Select the “Create a new platform from hardware (XSA)” tab and click browse to select the XSA file you saved earlier:
 
-    ![Adding the XSA file](images/picture29.png) 
+    ![Screenshot of Vitis New Application Project wizard showing the Create a new platform from hardware (XSA) option with a browse button to select the exported hardware description file containing the FPGA design and processor configuration](images/picture29.png) 
 
     *Figure 3.7. Adding the XSA file*