reviewing memory subsystem with ASCT

Author: jasonrandrews

content/learning-paths/servers-and-cloud-computing/memory-subsystem/cache-hierarchy.md

@@ -8,7 +8,7 @@ layout: learningpathall
 
 ## Why cache hierarchy matters
 
-Every memory access from the CPU passes through a hierarchy of caches before reaching DRAM. Each level trades capacity for speed: L1 is tiny but fast, L2 is larger but slower, and L3 (or a system-level cache) is the largest on-chip cache but has the highest latency. Understanding this hierarchy for your specific system tells you where performance "cliffs" will occur as your working set grows.
+Each memory access is satisfied by the closest level of the hierarchy that contains the requested data. If the data is not found in the private caches, the request falls through to lower levels and eventually to DRAM. Each level trades capacity for speed: L1 is tiny but fast, L2 is larger but slower, and L3 (or a system-level cache) is the largest on-chip cache but has the highest latency. Understanding this hierarchy for your specific system tells you where performance "cliffs" will occur as your working set grows.
 
 ## Cache levels on Arm systems
 

content/learning-paths/servers-and-cloud-computing/memory-subsystem/comparative-analysis.md

@@ -169,7 +169,7 @@ The `loaded-latency` results reveal the latency-bandwidth tradeoff:
 
 Single-core bandwidth from `bandwidth-sweep` shows the throughput capacity at each cache level:
 
-- **L1 bandwidth** doubles on Graviton4 (321 vs 159 GB/s, +101%). Both cores have two 128-bit load ports, but V2 also has a dedicated 128-bit store port and runs at a higher clock speed.
+- **L1 bandwidth** doubles on Graviton4 (321 vs 159 GB/s, +101%). This likely reflects a combination of higher clock speed and microarchitectural throughput improvements in Neoverse V2.
 - **L2 bandwidth** improves by 29% on Graviton4 (95 vs 73 GB/s), due to the wider L2 fill path and microarchitectural improvements in V2.
 - **LLC bandwidth** more than doubles on Graviton4 (80 vs 36 GB/s, +123%), reflecting improvements in the interconnect and shared cache design.
 - **DRAM bandwidth (single core)** improves by 77% on Graviton4 (37 vs 21 GB/s). V2 supports more outstanding memory requests than N1, and DDR5 provides more bandwidth per channel than DDR4.

content/learning-paths/servers-and-cloud-computing/memory-subsystem/multicore-bandwidth.md

@@ -59,7 +59,7 @@ Several patterns emerge from the traffic type comparison:
 - **All Reads** gives the highest throughput because reads are simpler for the memory controller, with no write-back or write-allocate overhead.
 - **Read-write mixes** reduce throughput progressively as the write ratio increases. Writes require the controller to alternate between read and write bus turnarounds, and in write-allocate caches, writes typically trigger a read-for-ownership and eventual eviction, increasing traffic. Non-temporal writes can avoid this overhead.
 
-Graviton4 with DDR5 delivers roughly 2.7x the peak all-reads bandwidth of Graviton2 with DDR4 (465.5 vs 169.6 GB/s). The Graviton4 output also includes a non-temporal traffic pattern (2:1 Rd-Wr Non-Temporal), which bypasses the cache on writes and can be more efficient for pure streaming workloads.
+Graviton4 with DDR5 delivers roughly 2.7x the peak all-reads bandwidth of Graviton2 with DDR4 (465.5 vs 169.6 GB/s). The Graviton4 output also includes a non-temporal traffic pattern (2:1 Rd-Wr Non-Temporal), which can reduce cache allocation, cache pollution, and coherence overhead for streaming writes.
 
 Compare the "All Reads" figure with the theoretical peak bandwidth reported by `asct system-info` to see how close each system gets to its maximum. Well-configured systems typically achieve 85-95% of theoretical peak with all-read traffic.
 

content/learning-paths/servers-and-cloud-computing/memory-subsystem/pointer-chase-latency.md

@@ -8,7 +8,7 @@ layout: learningpathall
 
 ## The pointer-chase technique
 
-Cache and memory latency is the single most important metric for characterizing a memory subsystem. The standard technique is a pointer chase, a linked list where each node points to the next, and the CPU must complete each load before it can issue the next one. This creates a chain of dependent loads that defeats both hardware prefetching and out-of-order execution, revealing the true access latency at each cache level.
+Cache and memory latency is the single most important metric for characterizing a memory subsystem. The standard technique is a pointer chase, a linked list where each node points to the next, and the CPU must complete each load before it can issue the next one. This creates a chain of dependent loads that defeats both hardware prefetching and out-of-order execution, letting you measure the effective dependent-load latency for this access pattern at each level of the memory hierarchy.
 
 ## Why pointer chasing works
 

content/learning-paths/servers-and-cloud-computing/memory-subsystem/streaming-bandwidth.md

@@ -58,7 +58,7 @@ The `bandwidth-sweep` benchmark reports the bandwidth at the optimal data size f
 
 Key differences to look for between Graviton2 and Graviton4:
 
-- **L1 bandwidth**: Graviton4 shows roughly 2x the L1 bandwidth of Graviton2. Both cores have two 128-bit load ports, but V2 also has a dedicated 128-bit store port and runs at a higher clock speed, producing significantly higher absolute GB/s.
+- **L1 bandwidth**: Graviton4 shows roughly 2x the L1 bandwidth of Graviton2. This likely reflects a combination of higher clock speed and microarchitectural throughput improvements in Neoverse V2.
 - **L2 bandwidth**: V2's larger 2 MB L2 keeps more data in the fast private cache, and microarchitectural improvements on V2 also increase L2 fill bandwidth.
 - **LLC bandwidth**: Graviton4 more than doubles the LLC bandwidth of Graviton2, reflecting improvements in the interconnect and shared cache design on V2.
 - **DRAM bandwidth (single core)**: Graviton4 achieves higher single-core DRAM throughput because V2 supports more outstanding memory requests than N1, and DDR5 provides more bandwidth per channel than DDR4.
@@ -69,7 +69,7 @@ To convert GB/s to bytes per cycle, use your core's clock speed:
 
 $$\text{Bytes/cycle} = \frac{\text{GB/s} \times 10^9}{\text{Clock (Hz)}}$$
 
-This normalization lets you compare microarchitectural efficiency independent of clock speed. The benchmark measures combined load and store throughput, so the combined load and store throughput can exceed the read-only peak of the load ports alone of the two 128-bit load ports. V2's dedicated store port gives it an additional advantage in this measurement.
+This normalization lets you compare microarchitectural efficiency independent of clock speed. The benchmark measures combined load and store throughput, so the results reflect both the core's execution throughput and the details of the benchmark's access pattern rather than a simple read-only port limit.
 
 ## Additional ASCT bandwidth benchmarks