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@@ -192,64 +192,31 @@ Create `boards/arm/mps4/mps4_corstone320_fpga.dts` with the following content:
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This file defines the SoC peripherals for the MPS4 FPGA build and is included by `mps4_corstone320_fpga.dts`. It is not a standalone file — the `.dts` file pulls it in during compilation with `#include`.
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Create `boards/arm/mps4/mps4_common_soc_peripheral_fpga.dtsi` with the following content. This configures the 25 MHz peripheral clock, GPIO controllers, and two UART instances using the MPS4 peripheral addresses from the [SSE-320 FPGA Image for MPS4 Application Note](https://developer.arm.com/documentation/109762/0100/?lang=en):
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Create `boards/arm/mps4/mps4_common_soc_peripheral_fpga.dtsi` with the following content. This configures the 50 MHz peripheral clock and two UART instances using the MPS4 peripheral addresses from the [SSE-320 FPGA Image for MPS4 Application Note](https://developer.arm.com/documentation/109762/0100/?lang=en):
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```dts
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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gpio0: gpio@100000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x100000 0x1000>;
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interrupts = <69 3>;
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gpio-controller;
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#gpio-cells = <2>;
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uart0: uart@9303000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x9303000 0x1000>;
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interrupts = <34 3 49 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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gpio1: gpio@101000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x101000 0x1000>;
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interrupts = <70 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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uart0: uart@8203000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x8203000 0x1000>;
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interrupts = <34 3 33 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart1: uart@8204000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x8204000 0x1000>;
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interrupts = <36 3 35 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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gpio_led0: mps4_fpgaio@8202000 {
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compatible = "arm,mmio32-gpio";
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reg = <0x8202000 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <8>;
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};
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gpio_button: mps4_fpgaio@8202008 {
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compatible = "arm,mmio32-gpio";
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reg = <0x8202008 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <2>;
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direction-input;
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uart1: uart@9304000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x9304000 0x1000>;
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interrupts = <36 3 35 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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pinctrl: pinctrl {
@@ -258,19 +225,6 @@ pinctrl: pinctrl {
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};
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```
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### Kconfig
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`Kconfig`is the board-level Kconfig entry. It selects the SoC variant and configures board-level options based on the board target you pass to `west build`.
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The existing `boards/arm/mps4/Kconfig` already handles the FVP variants. Add the FPGA variant by appending the `select SOC_CORSTONE320` line so the file looks like this:
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```kconfig
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config BOARD_MPS4
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select BUILD_WITH_TFM if BOARD_MPS4_CORSTONE315_FVP_NS || BOARD_MPS4_CORSTONE320_FVP_NS
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select TRUSTED_EXECUTION_NONSECURE if BOARD_MPS4_CORSTONE315_FVP_NS || BOARD_MPS4_CORSTONE320_FVP_NS
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select USE_DT_CODE_PARTITION if BOARD_MPS4_CORSTONE315_FVP_NS || BOARD_MPS4_CORSTONE320_FVP_NS
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select SOC_CORSTONE320 if BOARD_MPS4_CORSTONE320_FPGA
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```
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### Kconfig.defconfig
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@@ -311,6 +265,18 @@ endif
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endif
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```
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### Kconfig.mps4
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`Kconfig.mps4`is the base software configuration for selecting SoC and other board and SoC related settings. Add the FPGA support in the file.
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```
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config BOARD_MPS4
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select SOC_SERIES_MPS4
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select SOC_MPS4_CORSTONE315 if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE315_FVP_NS
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select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS || BOARD_MPS4_CORSTONE320_FPGA
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```
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### mps4_corstone320_fpga_defconfig
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`mps4_corstone320_fpga_defconfig` is a Kconfig fragment that Zephyr merges into the final `.config` when building for this board target. It enables TrustZone, MPU support, GPIO, and console over UART, and configures the build as a Secure image with ROM-region relocation.
Copy file name to clipboardExpand all lines: content/learning-paths/embedded-and-microcontrollers/zephyr_cs320_mps4/how-to-3.md
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@@ -28,7 +28,7 @@ Replace the path with your actual toolchain directory. On x86_64, the directory
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From the `~/zephyrproject/zephyr` directory, build the `hello_world` example for the Corstone-320 FPGA variant:
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```bash
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west build -p always -b mps4/corstone320/fpga samples/hello_world
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west build -p always -b mps4/corstone320/fpga zephyr/samples/hello_world -- -DCONFIG_ROMSTART_RELOCATION_ROM=y
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```
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A successful build ends with output similar to:
@@ -62,8 +62,8 @@ The ELF image contains the application and the Zephyr kernel libraries. You can
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For the hello_world application, place the vector table in the FPGA boot ROM at address `0x11000000`, and place the remaining code and data in SRAM at address `0x31000000`. Use `arm-none-eabi-objcopy` to extract these two regions from `zephyr.elf`:
Update `images.txt` under `/MB/HBI0376B/FI101` to load the two images. The paths use the `\SOFTWARE\` folder on the MPS4 SD card, which is where you will copy the binary files:
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