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title: Migrating SIMD code to the Arm architecture
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title: "Migrating SIMD code to the Arm architecture"
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# FIXED, DO NOT MODIFY
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## Vectorization on x86 and Arm
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Migrating SIMD (Single Instruction, Multiple Data) code from x86 extensions to Arm extensions is an important task for software developers aiming to optimize performance on Arm platforms.
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Understanding the mapping between x86 instruction sets like SSE, AVX, and AMX to Arm's NEON, SVE, and SME extensions is essential for ensuring portability and high performance. This Learning Path provides an overview to help you design a migration plan, leveraging Arm features such as scalable vector lengths and advanced matrix operations, to effectively adapt your code.
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Understanding the mapping from x86 instruction sets such as SSE, AVX, and AMX to Arm’s NEON, SVE, and SME extensions is essential for achieving portability and high performance. This Learning Path provides an overview to help you design a migration plan, leveraging Arm features such as scalable vector lengths and advanced matrix operations to adapt your code effectively.
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Vectorization is a key optimization strategy where one instruction processes multiple data elements simultaneously. It drives performance in HPC, AI/ML, signal processing, and data analytics.
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Vectorization is a key optimization strategy where one instruction processes multiple data elements simultaneously. It drives performance in High-Performance Computing (HPC), AI and ML, signal processing, and data analytics.
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Both x86 and Arm processors offer rich SIMD capabilities, but they differ in philosophy and design. The x86 architecture provides fixed-width vector units of 128, 256, and 512 bits. The Arm architecture offers a mix of fixed-width, for NEON, and scalable vectors for SVE and SME ranging from 128 to 2048 bits.
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Both x86 and Arm processors offer rich SIMD capabilities, but they differ in philosophy and design. The x86 architecture provides fixed-width vector units of 128, 256, and 512 bits. The Arm architecture offers fixed-width vectors for NEONand scalable vectors for SVE and SME, ranging from 128 to 2048 bits.
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If you are interested in migrating SIMD software to Arm, understanding these differences ensures portable, high-performance code.
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If you are migrating SIMD software to Arm, understanding these differences helps you write portable, high-performance code.
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## Arm vector and matrix extensions
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### NEON
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NEON is a 128‑bit SIMD extension available across Armv8‑A cores (including Neoverse and mobile). It is well suited to multimedia, DSP, and packet processing. Conceptually, NEON is closest to x86 SSE (and AVX used in 128‑bit mode), making it the primary target when migrating SSE workloads. Compiler auto‑vectorization to NEON is mature, reducing the need for manual intrinsics.
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NEON is a 128-bit SIMD extension available across Armv8-A cores, including Neoverse and mobile. It is well suited to multimedia, DSP, and packet processing. Conceptually, NEON is closest to x86 SSE and AVX used in 128-bit mode, making it the primary target when migrating many SSE workloads. Compiler auto-vectorization to NEON is mature, reducing the need for manual intrinsics.
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### Scalable Vector Extension (SVE)
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SVE introduces a revolutionary approach to SIMD with its vector-length agnostic (VLA) design. Registers in SVE can range from 128 to 2048 bits, with the exact width determined by the hardware implementation in multiples of 128 bits. This flexibility allows the same binary to run efficiently across different hardware generations. SVE also features advanced capabilities like per-element predication, which eliminates branch divergence, and native support for gather/scatter operations, enabling efficient handling of irregular memory accesses. While SVE is ideal for high-performance computing (HPC) and future-proof portability, developers must adapt to its unique programming model, which differs significantly from fixed-width SIMD paradigms. SVE is most similar to AVX-512 on x86, offering greater portability and scalability.
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### Scalable Matrix Extension (SME)
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SME is designed to accelerate matrix multiplication and is similar to AMX. Unlike AMX, which relies on dot-product-based operations, SME employs outer-product-based operations, providing greater flexibility for custom AI and HPC kernels. SME integrates seamlessly with SVE, utilizing scalable tiles and a streaming mode to optimize performance. It is particularly well-suited for AI training and inference workloads, as well as dense linear algebra in HPC applications.
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SME accelerates matrix multiplication and is similar in intent to AMX. Unlike AMX, which often uses dot-product oriented operations, SME employs outer-product oriented operations. SME integrates with SVE, using scalable tiles and a streaming mode to optimize performance. It is wellsuited to AI training and inference, as well as dense linear algebra in HPC applications.
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## x86 vector and matrix extensions
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### Advanced Vector Extensions (AVX)
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AVX introduces 256‑bit YMM registers and AVX‑512 adds 512‑bit ZMM registers. Features include FMA, mask registers (AVX‑512), and VEX/EVEX encodings. Migrating AVX code to Arm typically maps 128‑bit work to NEON and vector‑scalable algorithms to SVE. Because SVE is VLA, refactoring for predication and scalable loops is recommended.
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AVX provides 256-bit YMM registers, and AVX-512 adds 512-bit ZMM registers. Features include FMA, per-lane masking in AVX-512, and VEX or EVEX encodings. When moving AVX workloads to Arm, 128-bit paths often translate to NEON, while algorithms that scale with vector width are good candidates for SVE. Because SVE is vector-length agnostic, refactor for predication and scalable loops to maintain portability and performance.
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### Advanced Matrix Extensions (AMX)
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AMX accelerates matrix operations with **tile** registers configured via a tile palette. It suits AI workloads such as GEMM and convolutions. When migrating AMX kernels to Arm, target SME. While both target matrix compute, AMX commonly expresses **dot products**; SME focuses on **outer products**, so porting often entails algorithmic adjustments.
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AMX accelerates matrix operations with tile registers configured using a tile palette. It suits AI workloads such as GEMM and convolutions. When migrating AMX kernels to Arm, target SME. While both target matrix compute, AMX commonly expresses dot products, while SME focuses on outer products, so porting often entails algorithmic adjustments.
|**Best suited for**| HPC, AI and ML, scientific computing, analytics | HPC, AI and ML, scientific computing, cloud and scalable workloads |
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|**Limitations**| Power and thermal headroom under heavy 512-bit use; ecosystem complexity | Requires VLA programming style; SVE or SVE2 hardware availability varies by platform |
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{{% notice Note %}}
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SVE2 extends SVE with richer integer and DSP capabilities for general-purpose and media workloads.
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{{% /notice %}}
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### AMX vs. SME
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| Feature | x86: AMX | Arm: SME |
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|**Register model**| Tile registers configured via a palette; fixed per‑type limits | Scalable matrix tiles integrated with SVE; implementation‑dependent dimensions |
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|**Register model**| Tile registers configured via a palette; fixed pertype limits | Scalable matrix tiles integrated with SVE; implementation-dependent dimensions |
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|**Vector length model**| Fixed tile geometry per configuration | Scales with SVE vector length and streaming mode |
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|**Predication / masking**| Predication not inherent to tiles | Predication via SVE predicate registers |
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|**Gather / scatter**| Not provided in AMX tiles (handled elsewhere)| Via SVE integration (gather/scatter)|
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|**Key operations**| Dot‑product‑oriented GEMM/convolution | Outer‑product matrix multiply; streaming mode for dense linear algebra |
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|**Best suited for**| AI/ML training and inference, GEMM/conv kernels | AI/ML training and inference, scientific/HPC dense linear algebra |
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|**Limitations**| Hardware/software availability limited to specific CPUs | Emerging hardware support; compiler/library support evolving |
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|**Predication or masking**| Predication not inherent to tiles | Predication via SVE predicate registers |
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|**Gather or scatter**| Not provided in AMX tiles; handled elsewhere | Via SVE integration with gather or scatter |
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|**Key operations**| Dot-productoriented GEMM and convolution | Outer-product matrix multiply; streaming mode for dense linear algebra |
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|**Best suited for**| AI and ML training and inference, GEMM and convolution kernels | AI and ML training and inference, scientific and HPC dense linear algebra |
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|**Limitations**| Hardware and software availability limited to specific CPUs | Emerging hardware support; compiler and library support evolving |
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## Key differences for developers
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### Vector length model
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x86 SIMD (SSE/AVX/AVX‑512) uses fixed widths (128/256/512). This often requires multiple code paths or dispatch strategies. Arm NEON is also fixed at 128‑bit and is a familiar baseline. **SVE/SME** introduce **vector‑length agnostic** execution from 128 to 2048 bits so the same binary scales across implementations.
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x86 SIMD (SSE, AVX, and AVX-512) uses fixed widths of 128, 256, or 512 bits. This often requires multiple code paths or dispatch strategies. Arm NEON is also fixed at 128-bit and is a familiar baseline. SVE and SME introduce vector-length agnostic execution from 128 to 2048 bits so the same binary scales across implementations.
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### Programming and intrinsics
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x86 intrinsics are extensive, and AVX‑512 adds masks and lane controls that increase complexity. NEON intrinsics look familiar to SSE developers. SVE/SME use **predication** and scalable loops; prefer **auto‑vectorization** and VLA‑friendly patterns over heavy hand‑written intrinsics when portability matters.
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x86 intrinsics are extensive, and AVX-512 adds masks and lane controls that increase complexity. NEON intrinsics look familiar to SSE developers. SVE and SME use predication and scalable loops. Prefer auto-vectorization and VLA-friendly patterns over heavy hand-written intrinsics when portability matters.
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### Matrix acceleration
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AMX provides fixed‑geometry tile compute optimized for dot products. SME extends Arm’s scalable model with outer‑product math, scalable tiles, and streaming mode. Both AMX and SME are currently available on a **limited set of platforms**.
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AMX provides fixed-geometry tile compute optimized for dot products. SME extends Arm’s scalable model with outer-product math, scalable tiles, and streaming mode. Both AMX and SME are currently available on a limited set of platforms.
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### Overall summary
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Migrating from x86 SIMD to Arm entails adopting Arm’s **scalable** and **predicated** programming model (SVE/SME) for forward‑portable performance, while continuing to use NEON for fixed‑width SIMD similar to SSE.
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Migrating from x86 SIMD to Arm entails adopting Arm’s scalable and predicated programming model with SVE and SME for forward-portable performance, while continuing to use NEON for fixed-width SIMD similar to SSE.
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## Migration tools
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Several libraries help translate or abstract SIMD intrinsics to speed up migration. Coverage varies, and some features have no direct analogue.
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-**sse2neon**— Open‑source header that maps many SSE2 intrinsics to NEON equivalents. Good for getting code building quickly; still review generated code for performance. <https://github.com/DLTcollab/sse2neon>
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-**SIMD Everywhere (SIMDe)**— Header‑only portability layer that implements many x86/Arm intrinsics across ISAs, with scalar fallbacks when SIMD is unavailable. <https://github.com/simd-everywhere/simde>
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-**Google Highway (hwy)**— Portable SIMD library and APIs that target multiple ISAs (NEON, SVE where supported, AVX, etc.) for high‑performance data processing without per‑ISA code paths. <https://github.com/google/highway>
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-**sse2neon:**open-source header that maps many SSE2 intrinsics to NEON equivalents. Good for getting code building quickly. Review generated code for performance. <https://github.com/DLTcollab/sse2neon>
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-**SIMD Everywhere (SIMDe):**header-only portability layer that implements many x86 and Arm intrinsics across ISAs, with scalar fallbacks when SIMD is unavailable. <https://github.com/simd-everywhere/simde>
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-**Google Highway (hwy):**portable SIMD library and APIs that target multiple ISAs, including NEON, SVE where supported, and AVX, without per-ISA code paths. <https://github.com/google/highway>
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For more on cross‑platform intrinsics, see [Porting architecture‑specific intrinsics](/learning-paths/cross-platform/intrinsics/).
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For more on cross-platform intrinsics, see [Porting architecture-specific intrinsics](/learning-paths/cross-platform/intrinsics/).
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