Merge pull request #3062 from madeline-underwood/ipex

Enhance descriptions and image captions in IP Explorer documentation …

Author: pareenaverma

content/learning-paths/cross-platform/ipexplorer/_index.md

@@ -1,5 +1,6 @@
 ---
 title: Custom software for simulation with IP Explorer
+description: Learn how to run custom software benchmarks on IP Explorer simulation platforms and compare performance across Arm Cortex-M processors using cycle count analysis.
 minutes_to_complete: 60
 
 who_is_this_for: This is an introductory topic for IP Explorer users using the software simulation platforms available.

content/learning-paths/cross-platform/ipexplorer/custom2.md

@@ -37,11 +37,11 @@ The Cortex-M7 used in the simulation includes a Floating-Point Unit (FPU) which
 
 #### Cortex-M0
 
-![Cortex-M0 Simulation results #center](images/m0_custom.png)
+![Screenshot of IP Explorer simulation results for Cortex-M0 running the custom floating-point benchmark. The results show the processor used a C library software routine for floating-point operations since the Cortex-M0 does not include a hardware FPU, resulting in higher cycle counts.#center](images/m0_custom.png)
 
 #### Cortex-M7
 
-![Cortex-M7 Simulation results #center](images/m7_custom.png)
+![Screenshot of IP Explorer simulation results for Cortex-M7 running the custom floating-point benchmark. The results demonstrate significantly improved performance as the Cortex-M7's hardware FPU executes floating-point additions directly without requiring software emulation.#center](images/m7_custom.png)
 
 ## Show details
 

content/learning-paths/cross-platform/ipexplorer/preinstall.md

@@ -58,11 +58,11 @@ The exact cycle count may vary depending on compiler version used.
 
 #### Cortex-M0
 
-![Cortex-M0 Simulation results #center](images/m0_matrix-add.png)
+![Screenshot of IP Explorer simulation results for Cortex-M0 running the matrix addition example. The results panel shows marked software cycles indicating the execution time for the benchmark. This baseline measurement will be compared against Cortex-M7 performance.#center](images/m0_matrix-add.png)
 
 #### Cortex-M7
 
-![Cortex-M7 Simulation results #center](images/m7_matrix-add.png)
+![Screenshot of IP Explorer simulation results for Cortex-M7 running the matrix addition example. The results panel shows marked software cycles significantly lower than the Cortex-M0, demonstrating the performance improvement from the more advanced processor architecture.#center](images/m7_matrix-add.png)
 
 
 You can click `Show details` to get a deeper understanding of the data. You will return to this when custom software is used.