🚀 SystemVerilog Valid-Ready Pipeline Verification

Backpressure-aware, lossless 1-stage streaming pipeline
_{(Elastic Buffer / AXI-Stream Register Slice Equivalent)}

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⚡ Executive Summary

Aspect	Detail
Problem	Reliable data transfer under backpressure
Solution	1-stage valid-ready pipeline (elastic buffer)
Guarantee	No data loss, no overwrite, in-order delivery
Latency	1 cycle
Throughput	1 txn / cycle (no stalls)
Result	PASS 20 / 20

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🧩 Problem Statement

In synchronous digital systems, producer and consumer operate at independent rates. Without proper flow control:

• ❌ Data loss under backpressure
• ❌ Overwrite of unconsumed data
• ❌ Ordering violations
• ❌ Non-deterministic throughput

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🎯 Objective

Design and verify a pipeline stage that:

• ✔ Guarantees lossless transfer
• ✔ Handles arbitrary backpressure
• ✔ Preserves strict ordering
• ✔ Ensures cycle-accurate deterministic behavior

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🔗 Protocol Definition

A transaction occurs iff:

valid && ready

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🧠 Architecture

flowchart LR

    %% =========================
    %% DATA PATH
    %% =========================
    P[Producer] -->|data| B[Pipeline Register]
    B -->|data| C[Consumer]

    %% =========================
    %% CONTROL SIGNALS
    %% =========================
    P -->|valid| B
    C -->|ready| B

    %% =========================
    %% STATE MACHINE (TIED TO PIPELINE)
    %% =========================
    E[EMPTY slot_full=0] -->|valid| F[FULL slot_full=1]
    F -->|ready| E

    F -.holds data.-> B

    %% =========================
    %% CORE BEHAVIOR (MATCHES TIMING)
    %% =========================
    B -->|valid & ready → transfer| C
    B -->|valid & !ready → hold| B

    %% =========================
    %% INVARIANTS (MATCHES SVA)
    %% =========================
    I1[Transfer iff valid AND ready]
    I2[Data stable when valid AND NOT ready]

    I1 --> B
    I2 --> B

Loading

Equivalent to a 1-depth elastic buffer / AXI-Stream register slice

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🏗️ Design Summary

Component	Role
data_reg	Holds current transaction
slot_full	Indicates valid data present
txn_count	Counts completed transfers

Behavior

Condition	Action
full + ready	consume
empty + valid	load
full + !ready	stall (hold data)

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🧪 Verification Strategy

Architecture

• Generator
• Driver
• Monitor
• Scoreboard (mailbox-based)

Stimulus

• Random data
• Random delay (1–5 cycles)
• Random backpressure (0–8 cycles)

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🧷 Assertions (SVA)

// Transfer occurs only on handshake
property handshake_transfer;
  @(posedge clk) (valid && ready) |-> ##1 txn_count == $past(txn_count) + 1;
endproperty
assert property (handshake_transfer);

// Data must remain stable under backpressure
property data_stable_on_stall;
  @(posedge clk) (valid && !ready) |-> $stable(data_reg);
endproperty
assert property (data_stable_on_stall);

// No overwrite before consumption
property no_overwrite;
  @(posedge clk) (slot_full && !ready) |-> $stable(data_reg);
endproperty
assert property (no_overwrite);

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📊 Functional Coverage

covergroup handshake_cg @(posedge clk);
  coverpoint valid;
  coverpoint ready;
  cross valid, ready;
endgroup

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⏱️ Timing Behavior

Clock      ─┐_┌─┐_┌─┐_┌─┐_┌─┐_┌─┐_┌─┐_┌─┐

valid      ──■■■■■■■■────■■■■■■■■────────
ready      ─────■■■■■■■■──────■■■■■■────
data       === A === B === B === C === D ===

handshake     ↑     ↑        ↑     ↑
              A     B        C     D

txn_count     0 → 1 → 2 → 2 → 3 → 4

Interpretation

• ✔ Transfer only when valid && ready
• ✔ Data stable during stall
• ✔ No overwrite
• ✔ Count increments only on handshake

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📈 Waveform Evidence

✔ Handshake correctness ✔ Backpressure handling ✔ Stable data ✔ In-order execution

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📌 Verification Results

Metric	Status
Transactions	20
PASS	20
FAIL	0
Assertions	PASS
Data Integrity	Verified

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⚙️ Performance

Metric	Value
Latency	1 cycle
Throughput	1 txn/cycle
Backpressure	Lossless

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▶️ How to Run

xvlog src/pipeline_dut.sv sim/transaction.sv sim/tb_pipeline.sv
xelab tb_pipeline -s tb_pipeline_sim
xsim tb_pipeline_sim -run all

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📁 Repository Structure

src/
 └── pipeline_dut.sv

sim/
 ├── tb_pipeline.sv
 └── transaction.sv

waveform.png
README.md
.gitignore

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🏭 Industry Relevance

• AXI-Stream pipelines
• Network-on-Chip routers
• DSP streaming systems
• FIFO front-end buffering

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🔮 Extensions

• Multi-stage FIFO
• Skid buffer design
• AXI-Stream wrapper
• UVM verification environment
• Coverage closure metrics

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🧠 Design Invariants

1. Transfer ⇔ valid && ready
2. Data stable when valid && !ready
3. No overwrite before consumption
4. txn_count increments only on handshake

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👤 Author

Arya Dinesh
B.Tech Electronics & Communication Engineering

📫 Let’s connect: www.linkedin.com/in/aryadinesh2005

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⭐ If you found this project interesting, feel free to star this repository!
🧠 Open for collaboration or discussion on FPGA, digital design, and embedded systems.

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