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control_emulator.xml
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3 lines (3 loc) · 66.7 KB
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<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE document SYSTEM "file:///C:/Xilinx/14.7/ISE_DS/ISE/xpla3/data/xmlReportxpla3.dtd">
<document><ascFile>control_emulator.rpt</ascFile><devFile>C:/Xilinx/14.7/ISE_DS/ISE/xpla3/data/xcr3064xl.chp</devFile><mfdFile>control_emulator.mfd</mfdFile><htmlFile logic_legend="logiclegend.htm" logo="coolrunner_logo.jpg" pin_legend="pinlegend.htm"/><header date=" 6-29-2016" design="control_emulator" device="XCR3064XL" eqnType="1" pkg="VQ44" speed="-10" status="1" statusStr="Successful" swVersion="P.20131013" time=" 4:25PM" version="1.0"/><inputs id="GPIO_Extra0" userloc="P28"/><inputs id="aux2" userloc="P22"/><inputs id="aux3" userloc="P23"/><inputs id="aux_in" userloc="P30"/><inputs id="pgood"/><inputs id="mode_select" userloc="P2"/><inputs id="clk_select" userloc="P44"/><inputs id="qie_reset_in"/><inputs id="qie_reset_source"/><inputs id="reset_switch" userloc="P25"/><inputs id="xPUP_0"/><global_inputs id="int_clk_in" use="GCK" userloc="P39"/><global_inputs id="ext_clk_in" use="GCK" userloc="P38"/><global_inputs id="clk_in_j1" use="GCK" userloc="P37"/><pin id="FB1_MC1_PIN35" pinnum="35" signal="qie_reset_in" use="I"/><pin id="FB1_MC2_PIN34" pinnum="34" signal="miscControlsdelay_reg3_SPECSIG" use="b_SPECSIG"/><pin id="FB1_MC8_PIN33" pinnum="33" signal="miscControlsdelay_reg2_SPECSIG" use="b_SPECSIG"/><pin id="FB1_MC9_PIN32" pinnum="32" signal="fcl_extClk_extCtrlhold1_SPECSIG" use="b_SPECSIG"/><pin id="FB1_MC10_PIN31" pinnum="31" signal="penable" use="O"/><pin id="FB1_MC11_PIN30" pinnum="30" signal="pgood" use="I"/><pin id="FB1_MC14_PIN28" pinnum="28" signal="GPIO_Extra0" use="I"/><pin id="FB1_MC15_PIN27" pinnum="27" signal="clk_out_p2" use="O"/><pin id="FB2_MC1_PIN42" pinnum="42" signal="qie_reset_source" use="I"/><pin id="FB2_MC2_PIN43" pinnum="43" signal="fcl_intClk_intCtrlupcout2_SPECSIG" use="b_SPECSIG"/><pin id="FB2_MC3_PIN44" pinnum="44" signal="clk_select" use="I"/><pin id="FB2_MC9_PIN1" pinnum="1" signal="wte_out_intClk_intCtrl" use="b_SPECSIG"/><pin id="FB2_MC10_PIN2" pinnum="2" signal="mode_select" use="I"/><pin id="FB2_MC11_PIN3" pinnum="3" signal="reset_out" use="O"/><pin id="FB2_MC14_PIN5" pinnum="5" signal="qie_reset_out" use="O"/><pin id="FB2_MC15_PIN6" pinnum="6" signal="wte_out" use="O"/><pin id="FB3_MC1_PIN26" pinnum="26" signal="reset_out_intClk_intCtrl" use="b_SPECSIG"/><pin id="FB3_MC2_PIN25" pinnum="25" signal="reset_switch" use="I"/><pin id="FB3_MC4_PIN23" pinnum="23" signal="aux3" use="I"/><pin id="FB3_MC9_PIN22" pinnum="22" signal="aux2" use="I"/><pin id="FB3_MC10_PIN21" pinnum="21" signal="aux_out" use="O"/><pin id="FB3_MC11_PIN20" pinnum="20" signal="aux_in" use="I"/><pin id="FB3_MC12_PIN19" pinnum="19" signal="miscControlsdelay_reg14_SPECSIG" use="b_SPECSIG"/><pin id="FB3_MC13_PIN18" pinnum="18" signal="miscControlsdelay_reg13_SPECSIG" use="b_SPECSIG"/><pin id="FB4_MC1_PIN7" pinnum="7" signal="reset_out_intClk_extCtrl" use="b_SPECSIG"/><pin id="FB4_MC2_PIN8" pinnum="8" signal="peltEnab1" use="O"/><pin id="FB4_MC4_PIN10" pinnum="10"/><pin id="FB4_MC5_PIN11" pinnum="11" signal="peltEnab2" use="O"/><pin id="FB4_MC9_PIN12" pinnum="12"/><pin id="FB4_MC10_PIN13" pinnum="13"/><pin id="FB4_MC11_PIN14" pinnum="14"/><pin id="FB4_MC12_PIN15" pinnum="15"/><pin id="GLOBAL_PIN2" pinnum="39" signal="int_clk_in" use="GCK/I"/><pin id="GLOBAL_PIN3" pinnum="38" signal="ext_clk_in" use="GCK/I"/><pin id="GLOBAL_PIN4" pinnum="37" signal="clk_in_j1" use="GCK/I"/><uct bct="FB1_bct7" id="UCT1"/><fblock id="FB1" pinUse="5"><macrocell id="FB1_MC1" pin="FB1_MC1_PIN35" sigUse="6" signal="miscControlsdelay_reg4_SPECSIG"><eq_pterm ptindx="FB1_8"/></macrocell><macrocell id="FB1_MC2" pin="FB1_MC2_PIN34" sigUse="5" signal="miscControlsdelay_reg3_SPECSIG"><eq_pterm ptindx="FB1_10"/></macrocell><macrocell id="FB1_MC3" sigUse="2" signal="fcl_intClk_extCtrlhold2_SPECSIG"><eq_pterm ptindx="FB1_12"/></macrocell><macrocell id="FB1_MC4" sigUse="3" signal="fcl_intClk_extCtrlhold3_SPECSIG"><eq_pterm ptindx="FB1_14"/></macrocell><macrocell id="FB1_MC5" sigUse="6" signal="qie_reset_out_intClk_extCtrl"><eq_pterm ptindx="FB1_9"/><eq_pterm ptindx="FB1_11"/></macrocell><macrocell id="FB1_MC6" sigUse="5" signal="fcl_intClk_extCtrlhold0_SPECSIG"><eq_pterm ptindx="FB1_18"/></macrocell><macrocell id="FB1_MC7" sigUse="6" signal="qie_reset_out_extClk_extCtrl"><eq_pterm ptindx="FB1_5"/><eq_pterm ptindx="FB1_6"/></macrocell><macrocell id="FB1_MC8" pin="FB1_MC8_PIN33" sigUse="4" signal="miscControlsdelay_reg2_SPECSIG"><eq_pterm ptindx="FB1_22"/></macrocell><macrocell id="FB1_MC9" pin="FB1_MC9_PIN32" sigUse="1" signal="fcl_extClk_extCtrlhold1_SPECSIG"><eq_pterm ptindx="FB1_24"/></macrocell><macrocell id="FB1_MC10" pin="FB1_MC10_PIN31" sigUse="3" signal="penable"><eq_pterm ptindx="FB1_4"/><eq_pterm ptindx="FB1_3"/></macrocell><macrocell id="FB1_MC11" pin="FB1_MC11_PIN30" sigUse="3" signal="miscControlsdelay_reg1_SPECSIG"><eq_pterm ptindx="FB1_28"/></macrocell><macrocell id="FB1_MC12" sigUse="5" signal="fcl_extClk_extCtrlhold0_SPECSIG"><eq_pterm ptindx="FB1_30"/></macrocell><macrocell id="FB1_MC13" sigUse="3" signal="fcl_extClk_extCtrlhold3_SPECSIG"><eq_pterm ptindx="FB1_32"/></macrocell><macrocell id="FB1_MC14" pin="FB1_MC14_PIN28" sigUse="1" signal="fcl_intClk_extCtrlhold1_SPECSIG"><eq_pterm ptindx="FB1_34"/></macrocell><macrocell id="FB1_MC15" pin="FB1_MC15_PIN27" sigUse="5" signal="clk_out_p2"><eq_pterm ptindx="FB1_2"/><eq_pterm ptindx="FB1_0"/><eq_pterm ptindx="FB1_1"/></macrocell><macrocell id="FB1_MC16" sigUse="2" signal="fcl_extClk_extCtrlhold2_SPECSIG"><eq_pterm ptindx="FB1_38"/></macrocell><fbinput id="FB1_I1" signal="N_PZ_303"/><fbinput id="FB1_I2" signal="aux_in"/><fbinput id="FB1_I3" signal="clk_in_j1"/><fbinput id="FB1_I4" signal="clk_out_p2"/><fbinput id="FB1_I5" signal="clk_select"/><fbinput id="FB1_I6" signal="ext_clk_in"/><fbinput id="FB1_I7" signal="fcl_extClk_extCtrlhold0_SPECSIG"/><fbinput id="FB1_I8" signal="fcl_extClk_extCtrlhold1_SPECSIG"/><fbinput id="FB1_I9" signal="fcl_extClk_extCtrlhold2_SPECSIG"/><fbinput id="FB1_I10" signal="fcl_extClk_extCtrlhold3_SPECSIG"/><fbinput id="FB1_I11" signal="fcl_intClk_extCtrlhold0_SPECSIG"/><fbinput id="FB1_I12" signal="fcl_intClk_extCtrlhold1_SPECSIG"/><fbinput id="FB1_I13" signal="fcl_intClk_extCtrlhold2_SPECSIG"/><fbinput id="FB1_I14" signal="fcl_intClk_extCtrlhold3_SPECSIG"/><fbinput id="FB1_I15" signal="int_clk_in"/><fbinput id="FB1_I16" signal="miscControlsdelay_reg0_SPECSIG"/><fbinput id="FB1_I17" signal="miscControlsdelay_reg1_SPECSIG"/><fbinput id="FB1_I18" signal="miscControlsdelay_reg2_SPECSIG"/><fbinput id="FB1_I19" signal="miscControlsdelay_reg3_SPECSIG"/><fbinput id="FB1_I20" signal="miscControlspenable_reg_SPECSIG"/><fbinput id="FB1_I21" signal="mode_select"/><fbinput id="FB1_I22" signal="qie_reset_in"/><fbinput id="FB1_I23" signal="qie_reset_out_extClk_extCtrl"/><fbinput id="FB1_I24" signal="qie_reset_out_intClk_extCtrl"/><PAL><pterm id="FB1_0"><signal id="int_clk_in" negated="ON"/><signal id="mode_select"/><signal id="clk_select"/></pterm><pterm id="FB1_1"><signal id="mode_select" negated="ON"/><signal id="clk_select"/><signal id="clk_in_j1" negated="ON"/></pterm><pterm id="FB1_2"><signal id="clk_select" negated="ON"/><signal id="ext_clk_in" negated="ON"/></pterm><pterm id="FB1_3"><signal id="mode_select" negated="ON"/><signal id="aux_in" negated="ON"/></pterm><pterm id="FB1_4"><signal id="mode_select"/><signal id="miscControlspenable_reg_SPECSIG" negated="ON"/></pterm><pterm id="FB1_5"><signal id="qie_reset_in" negated="ON"/><signal id="fcl_extClk_extCtrlhold0_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold1_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold2_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold3_SPECSIG" negated="ON"/></pterm><pterm id="FB1_6"><signal id="qie_reset_out_extClk_extCtrl"/><signal id="qie_reset_in"/><signal id="fcl_extClk_extCtrlhold0_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold1_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold2_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold3_SPECSIG" negated="ON"/></pterm><pterm id="FB1_7"><signal id="clk_out_p2"/></pterm><pterm id="FB1_8"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/></pterm><pterm id="FB1_9"><signal id="qie_reset_in" negated="ON"/><signal id="fcl_intClk_extCtrlhold0_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold1_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold2_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold3_SPECSIG" negated="ON"/></pterm><pterm id="FB1_10"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/><signal id="miscControlsdelay_reg2_SPECSIG"/></pterm><pterm id="FB1_11"><signal id="qie_reset_in"/><signal id="qie_reset_out_intClk_extCtrl"/><signal id="fcl_intClk_extCtrlhold0_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold1_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold2_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold3_SPECSIG" negated="ON"/></pterm><pterm id="FB1_12"><signal id="fcl_intClk_extCtrlhold0_SPECSIG"/><signal id="fcl_intClk_extCtrlhold1_SPECSIG"/></pterm><pterm id="FB1_14"><signal id="fcl_intClk_extCtrlhold0_SPECSIG"/><signal id="fcl_intClk_extCtrlhold1_SPECSIG"/><signal id="fcl_intClk_extCtrlhold2_SPECSIG"/></pterm><pterm id="FB1_18"><signal id="qie_reset_in"/><signal id="fcl_intClk_extCtrlhold0_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold1_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold2_SPECSIG" negated="ON"/><signal id="fcl_intClk_extCtrlhold3_SPECSIG" negated="ON"/></pterm><pterm id="FB1_22"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/></pterm><pterm id="FB1_24"><signal id="fcl_extClk_extCtrlhold0_SPECSIG"/></pterm><pterm id="FB1_28"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="N_PZ_303"/></pterm><pterm id="FB1_30"><signal id="qie_reset_in"/><signal id="fcl_extClk_extCtrlhold0_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold1_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold2_SPECSIG" negated="ON"/><signal id="fcl_extClk_extCtrlhold3_SPECSIG" negated="ON"/></pterm><pterm id="FB1_32"><signal id="fcl_extClk_extCtrlhold0_SPECSIG"/><signal id="fcl_extClk_extCtrlhold1_SPECSIG"/><signal id="fcl_extClk_extCtrlhold2_SPECSIG"/></pterm><pterm id="FB1_34"><signal id="fcl_intClk_extCtrlhold0_SPECSIG"/></pterm><pterm id="FB1_38"><signal id="fcl_extClk_extCtrlhold0_SPECSIG"/><signal id="fcl_extClk_extCtrlhold1_SPECSIG"/></pterm></PAL><bct id="FB1_bct0" use=""/><bct id="FB1_bct1" use=""/><bct id="FB1_bct2" use=""/><bct id="FB1_bct3" use=""/><bct id="FB1_bct4" use=""/><bct id="FB1_bct5" use=""/><bct id="FB1_bct6" use=""/><bct id="FB1_bct7" use="uct1"><eq_pterm ptindx="FB1_7"/></bct><equation id="miscControlsdelay_reg4_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_8"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg3_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_10"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_extCtrlhold2_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_12"/></d1><clk><fastsig signal="clk_in_j1"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_extCtrlhold3_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_14"/></d1><clk><fastsig signal="clk_in_j1"/></clk><prld ptindx="GND"/></equation><equation id="qie_reset_out_intClk_extCtrl"><d2><eq_pterm ptindx="FB1_9"/><eq_pterm ptindx="FB1_11"/></d2><clk><fastsig signal="clk_in_j1"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_extCtrlhold0_SPECSIG" negated="ON" regUse="T"><d1><eq_pterm ptindx="FB1_18"/></d1><clk><fastsig signal="clk_in_j1"/></clk><prld ptindx="GND"/></equation><equation id="qie_reset_out_extClk_extCtrl"><d2><eq_pterm ptindx="FB1_5"/><eq_pterm ptindx="FB1_6"/></d2><clk><fastsig signal="ext_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg2_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_22"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="fcl_extClk_extCtrlhold1_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_24"/></d1><clk><fastsig signal="ext_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="penable" negated="ON"><d2><eq_pterm ptindx="FB1_4"/><eq_pterm ptindx="FB1_3"/></d2></equation><equation id="miscControlsdelay_reg1_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_28"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="fcl_extClk_extCtrlhold0_SPECSIG" negated="ON" regUse="T"><d1><eq_pterm ptindx="FB1_30"/></d1><clk><fastsig signal="ext_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_extClk_extCtrlhold3_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_32"/></d1><clk><fastsig signal="ext_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_extCtrlhold1_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_34"/></d1><clk><fastsig signal="clk_in_j1"/></clk><prld ptindx="GND"/></equation><equation id="clk_out_p2" negated="ON"><d2><eq_pterm ptindx="FB1_2"/><eq_pterm ptindx="FB1_0"/><eq_pterm ptindx="FB1_1"/></d2></equation><equation id="fcl_extClk_extCtrlhold2_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB1_38"/></d1><clk><fastsig signal="ext_clk_in"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB2" pinUse="6"><macrocell id="FB2_MC1" pin="FB2_MC1_PIN42" sigUse="4" signal="fcl_intClk_intCtrlupcout1_SPECSIG"><eq_pterm ptindx="FB2_44"/><eq_pterm ptindx="FB2_43"/></macrocell><macrocell id="FB2_MC2" pin="FB2_MC2_PIN43" sigUse="5" signal="fcl_intClk_intCtrlupcout2_SPECSIG"><eq_pterm ptindx="FB2_40"/><eq_pterm ptindx="FB2_41"/><eq_pterm ptindx="FB2_42"/></macrocell><macrocell id="FB2_MC3" pin="FB2_MC3_PIN44" sigUse="6" signal="fcl_intClk_intCtrlupcout3_SPECSIG"><eq_pterm ptindx="FB2_36"/><eq_pterm ptindx="FB2_37"/><eq_pterm ptindx="FB2_39"/></macrocell><macrocell id="FB2_MC4" sigUse="8" signal="fcl_intClk_intCtrlupcout5_SPECSIG"><eq_pterm ptindx="FB2_30"/><eq_pterm ptindx="FB2_31"/><eq_pterm ptindx="FB2_32"/></macrocell><macrocell id="FB2_MC5" sigUse="9" signal="fcl_intClk_intCtrlupcout6_SPECSIG"><eq_pterm ptindx="FB2_27"/><eq_pterm ptindx="FB2_28"/><eq_pterm ptindx="FB2_29"/></macrocell><macrocell id="FB2_MC6" sigUse="10" signal="fcl_intClk_intCtrlupcout7_SPECSIG"><eq_pterm ptindx="FB2_24"/><eq_pterm ptindx="FB2_25"/><eq_pterm ptindx="FB2_26"/></macrocell><macrocell id="FB2_MC7" sigUse="11" signal="fcl_intClk_intCtrlupcout8_SPECSIG"><eq_pterm ptindx="FB2_21"/><eq_pterm ptindx="FB2_22"/><eq_pterm ptindx="FB2_23"/></macrocell><macrocell id="FB2_MC8" sigUse="12" signal="fcl_intClk_intCtrlupcout9_SPECSIG"><eq_pterm ptindx="FB2_18"/><eq_pterm ptindx="FB2_19"/><eq_pterm ptindx="FB2_20"/></macrocell><macrocell id="FB2_MC9" pin="FB2_MC9_PIN1" sigUse="15" signal="wte_out_intClk_intCtrl"><eq_pterm ptindx="FB2_9"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_11"/></macrocell><macrocell id="FB2_MC10" pin="FB2_MC10_PIN2" sigUse="7" signal="fcl_intClk_intCtrlupcout4_SPECSIG"><eq_pterm ptindx="FB2_33"/><eq_pterm ptindx="FB2_34"/><eq_pterm ptindx="FB2_35"/></macrocell><macrocell id="FB2_MC11" pin="FB2_MC11_PIN3" sigUse="5" signal="reset_out"><eq_pterm ptindx="FB2_4"/><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_5"/></macrocell><macrocell id="FB2_MC12" sigUse="13" signal="fcl_intClk_intCtrlupcout10_SPECSIG"><eq_pterm ptindx="FB2_15"/><eq_pterm ptindx="FB2_16"/><eq_pterm ptindx="FB2_17"/></macrocell><macrocell id="FB2_MC13" sigUse="14" signal="fcl_intClk_intCtrlupcout11_SPECSIG"><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_13"/><eq_pterm ptindx="FB2_14"/></macrocell><macrocell id="FB2_MC14" pin="FB2_MC14_PIN5" sigUse="7" signal="qie_reset_out"><eq_pterm ptindx="FB2_0"/><eq_pterm ptindx="FB2_1"/><eq_pterm ptindx="FB2_3"/><eq_pterm ptindx="FB2_2"/></macrocell><macrocell id="FB2_MC15" pin="FB2_MC15_PIN6" sigUse="4" signal="wte_out"><eq_pterm ptindx="FB2_7"/><eq_pterm ptindx="FB2_8"/></macrocell><macrocell id="FB2_MC16" sigUse="14" signal="qie_reset_out_intClk_intCtrl"><eq_pterm ptindx="FB2_38"/></macrocell><fbinput id="FB2_I1" signal="clk_select"/><fbinput id="FB2_I2" signal="ext_clk_in"/><fbinput id="FB2_I3" signal="fcl_intClk_intCtrlupcout0_SPECSIG"/><fbinput id="FB2_I4" signal="fcl_intClk_intCtrlupcout10_SPECSIG"/><fbinput id="FB2_I5" signal="fcl_intClk_intCtrlupcout11_SPECSIG"/><fbinput id="FB2_I6" signal="fcl_intClk_intCtrlupcout1_SPECSIG"/><fbinput id="FB2_I7" signal="fcl_intClk_intCtrlupcout2_SPECSIG"/><fbinput id="FB2_I8" signal="fcl_intClk_intCtrlupcout3_SPECSIG"/><fbinput id="FB2_I9" signal="fcl_intClk_intCtrlupcout4_SPECSIG"/><fbinput id="FB2_I10" signal="fcl_intClk_intCtrlupcout5_SPECSIG"/><fbinput id="FB2_I11" signal="fcl_intClk_intCtrlupcout6_SPECSIG"/><fbinput id="FB2_I12" signal="fcl_intClk_intCtrlupcout7_SPECSIG"/><fbinput id="FB2_I13" signal="fcl_intClk_intCtrlupcout8_SPECSIG"/><fbinput id="FB2_I14" signal="fcl_intClk_intCtrlupcout9_SPECSIG"/><fbinput id="FB2_I15" signal="mode_select"/><fbinput id="FB2_I16" signal="qie_reset_in"/><fbinput id="FB2_I17" signal="qie_reset_out_extClk_extCtrl"/><fbinput id="FB2_I18" signal="qie_reset_out_intClk_extCtrl"/><fbinput id="FB2_I19" signal="qie_reset_out_intClk_intCtrl"/><fbinput id="FB2_I20" signal="qie_reset_source"/><fbinput id="FB2_I21" signal="reset_out_extClk_extCtrl"/><fbinput id="FB2_I22" signal="reset_out_intClk_extCtrl"/><fbinput id="FB2_I23" signal="reset_out_intClk_intCtrl"/><fbinput id="FB2_I24" signal="wte_out_intClk_intCtrl"/><PAL><pterm id="FB2_0"><signal id="ext_clk_in"/><signal id="qie_reset_source"/></pterm><pterm id="FB2_1"><signal id="mode_select"/><signal id="clk_select"/><signal id="qie_reset_source" negated="ON"/><signal id="qie_reset_out_intClk_intCtrl"/></pterm><pterm id="FB2_2"><signal id="mode_select" negated="ON"/><signal id="clk_select" negated="ON"/><signal id="qie_reset_source" negated="ON"/><signal id="qie_reset_out_extClk_extCtrl" negated="ON"/></pterm><pterm id="FB2_3"><signal id="mode_select" negated="ON"/><signal id="clk_select"/><signal id="qie_reset_source" negated="ON"/><signal id="qie_reset_out_intClk_extCtrl"/></pterm><pterm id="FB2_4"><signal id="mode_select"/><signal id="clk_select"/><signal id="reset_out_intClk_intCtrl"/></pterm><pterm id="FB2_5"><signal id="mode_select" negated="ON"/><signal id="clk_select" negated="ON"/><signal id="reset_out_extClk_extCtrl"/></pterm><pterm id="FB2_6"><signal id="mode_select" negated="ON"/><signal id="clk_select"/><signal id="reset_out_intClk_extCtrl"/></pterm><pterm id="FB2_7"><signal id="mode_select" negated="ON"/><signal id="qie_reset_in" negated="ON"/></pterm><pterm id="FB2_8"><signal id="mode_select"/><signal id="clk_select"/><signal id="wte_out_intClk_intCtrl"/></pterm><pterm id="FB2_9"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="wte_out_intClk_intCtrl"/></pterm><pterm id="FB2_10"><signal id="reset_out_intClk_intCtrl"/><signal id="wte_out_intClk_intCtrl"/></pterm><pterm id="FB2_11"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout10_SPECSIG" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout7_SPECSIG" negated="ON"/><signal id="fcl_intClk_intCtrlupcout8_SPECSIG" negated="ON"/><signal id="fcl_intClk_intCtrlupcout9_SPECSIG" negated="ON"/><signal id="fcl_intClk_intCtrlupcout11_SPECSIG" negated="ON"/></pterm><pterm id="FB2_12"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout11_SPECSIG"/></pterm><pterm id="FB2_13"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout11_SPECSIG"/></pterm><pterm id="FB2_14"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout10_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout7_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout8_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout9_SPECSIG"/></pterm><pterm id="FB2_15"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout10_SPECSIG"/></pterm><pterm id="FB2_16"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout10_SPECSIG"/></pterm><pterm id="FB2_17"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout7_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout8_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout9_SPECSIG"/></pterm><pterm id="FB2_18"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout9_SPECSIG"/></pterm><pterm id="FB2_19"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout9_SPECSIG"/></pterm><pterm id="FB2_20"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout7_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout8_SPECSIG"/></pterm><pterm id="FB2_21"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout8_SPECSIG"/></pterm><pterm id="FB2_22"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout8_SPECSIG"/></pterm><pterm id="FB2_23"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout7_SPECSIG"/></pterm><pterm id="FB2_24"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout7_SPECSIG"/></pterm><pterm id="FB2_25"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout7_SPECSIG"/></pterm><pterm id="FB2_26"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/></pterm><pterm id="FB2_27"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/></pterm><pterm id="FB2_28"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/></pterm><pterm id="FB2_29"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/></pterm><pterm id="FB2_30"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/></pterm><pterm id="FB2_31"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/></pterm><pterm id="FB2_32"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/></pterm><pterm id="FB2_33"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/></pterm><pterm id="FB2_34"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG"/></pterm><pterm id="FB2_35"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/></pterm><pterm id="FB2_36"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/></pterm><pterm id="FB2_37"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/></pterm><pterm id="FB2_38"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout10_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG" negated="ON"/><signal id="fcl_intClk_intCtrlupcout3_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout4_SPECSIG" negated="ON"/><signal id="fcl_intClk_intCtrlupcout5_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout6_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout7_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout8_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout9_SPECSIG" negated="ON"/><signal id="fcl_intClk_intCtrlupcout11_SPECSIG"/></pterm><pterm id="FB2_39"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/></pterm><pterm id="FB2_40"><signal id="qie_reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/></pterm><pterm id="FB2_41"><signal id="reset_out_intClk_intCtrl"/><signal id="fcl_intClk_intCtrlupcout2_SPECSIG"/></pterm><pterm id="FB2_42"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/></pterm><pterm id="FB2_43"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG" negated="ON"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG"/></pterm><pterm id="FB2_44"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout1_SPECSIG" negated="ON"/></pterm></PAL><bct id="FB2_bct0" use=""/><bct id="FB2_bct1" use=""/><bct id="FB2_bct2" use=""/><bct id="FB2_bct3" use=""/><bct id="FB2_bct4" use=""/><bct id="FB2_bct5" use=""/><bct id="FB2_bct6" use=""/><bct id="FB2_bct7" use=""/><equation id="fcl_intClk_intCtrlupcout1_SPECSIG"><d2><eq_pterm ptindx="FB2_44"/><eq_pterm ptindx="FB2_43"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_40"/><eq_pterm ptindx="FB2_41"/><eq_pterm ptindx="FB2_42"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_36"/><eq_pterm ptindx="FB2_37"/><eq_pterm ptindx="FB2_39"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout5_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_30"/><eq_pterm ptindx="FB2_31"/><eq_pterm ptindx="FB2_32"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout6_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_27"/><eq_pterm ptindx="FB2_28"/><eq_pterm ptindx="FB2_29"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout7_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_24"/><eq_pterm ptindx="FB2_25"/><eq_pterm ptindx="FB2_26"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout8_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_21"/><eq_pterm ptindx="FB2_22"/><eq_pterm ptindx="FB2_23"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout9_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_18"/><eq_pterm ptindx="FB2_19"/><eq_pterm ptindx="FB2_20"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="wte_out_intClk_intCtrl"><d2><eq_pterm ptindx="FB2_9"/><eq_pterm ptindx="FB2_10"/><eq_pterm ptindx="FB2_11"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout4_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_33"/><eq_pterm ptindx="FB2_34"/><eq_pterm ptindx="FB2_35"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="reset_out"><d2><eq_pterm ptindx="FB2_4"/><eq_pterm ptindx="FB2_6"/><eq_pterm ptindx="FB2_5"/></d2></equation><equation id="fcl_intClk_intCtrlupcout10_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_15"/><eq_pterm ptindx="FB2_16"/><eq_pterm ptindx="FB2_17"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout11_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_12"/><eq_pterm ptindx="FB2_13"/><eq_pterm ptindx="FB2_14"/></d2><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="qie_reset_out"><d2><eq_pterm ptindx="FB2_0"/><eq_pterm ptindx="FB2_1"/><eq_pterm ptindx="FB2_3"/><eq_pterm ptindx="FB2_2"/></d2></equation><equation id="wte_out"><d2><eq_pterm ptindx="FB2_7"/><eq_pterm ptindx="FB2_8"/></d2></equation><equation id="qie_reset_out_intClk_intCtrl"><d1><eq_pterm ptindx="FB2_38"/></d1><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB3" pinUse="5"><macrocell id="FB3_MC1" pin="FB3_MC1_PIN26" sigUse="1" signal="reset_out_intClk_intCtrl"><eq_pterm ptindx="FB3_8"/></macrocell><macrocell id="FB3_MC2" pin="FB3_MC2_PIN25" sigUse="19" signal="miscControlsdelay_reg17_SPECSIG"><eq_pterm ptindx="FB3_9"/><eq_pterm ptindx="FB3_10"/></macrocell><macrocell id="FB3_MC3" sigUse="13" signal="miscControlsdelay_reg12_SPECSIG"><eq_pterm ptindx="FB3_12"/></macrocell><macrocell id="FB3_MC4" pin="FB3_MC4_PIN23" sigUse="19" signal="miscControlsdelay_reg18_SPECSIG"><eq_pterm ptindx="FB3_14"/></macrocell><macrocell id="FB3_MC5" sigUse="12" signal="miscControlsdelay_reg11_SPECSIG"><eq_pterm ptindx="FB3_16"/></macrocell><macrocell id="FB3_MC6" sigUse="10" signal="miscControlsdelay_reg9_SPECSIG"><eq_pterm ptindx="FB3_18"/></macrocell><macrocell id="FB3_MC7" sigUse="8" signal="miscControlsdelay_reg7_SPECSIG"><eq_pterm ptindx="FB3_20"/></macrocell><macrocell id="FB3_MC8" sigUse="7" signal="miscControlsdelay_reg6_SPECSIG"><eq_pterm ptindx="FB3_22"/></macrocell><macrocell id="FB3_MC9" pin="FB3_MC9_PIN22" sigUse="18" signal="miscControlsdelay_reg16_SPECSIG"><eq_pterm ptindx="FB3_6"/><eq_pterm ptindx="FB3_7"/></macrocell><macrocell id="FB3_MC10" pin="FB3_MC10_PIN21" sigUse="1" signal="aux_out"><eq_pterm ptindx="FB3_26"/></macrocell><macrocell id="FB3_MC11" pin="FB3_MC11_PIN20" sigUse="17" signal="miscControlsdelay_reg15_SPECSIG"><eq_pterm ptindx="FB3_4"/><eq_pterm ptindx="FB3_5"/></macrocell><macrocell id="FB3_MC12" pin="FB3_MC12_PIN19" sigUse="16" signal="miscControlsdelay_reg14_SPECSIG"><eq_pterm ptindx="FB3_2"/><eq_pterm ptindx="FB3_3"/></macrocell><macrocell id="FB3_MC13" pin="FB3_MC13_PIN18" sigUse="15" signal="miscControlsdelay_reg13_SPECSIG"><eq_pterm ptindx="FB3_0"/><eq_pterm ptindx="FB3_1"/></macrocell><macrocell id="FB3_MC14" sigUse="6" signal="miscControlsdelay_reg5_SPECSIG"><eq_pterm ptindx="FB3_34"/></macrocell><macrocell id="FB3_MC15" sigUse="3" signal="fcl_intClk_intCtrlupcout0_SPECSIG"><eq_pterm ptindx="FB3_36"/></macrocell><macrocell id="FB3_MC16" sigUse="2" signal="reset_out_extClk_extCtrl"><eq_pterm ptindx="FB3_38"/></macrocell><fbinput id="FB3_I1" signal="GPIO_Extra0"/><fbinput id="FB3_I2" signal="N_PZ_303"/><fbinput id="FB3_I3" signal="fcl_intClk_intCtrlupcout0_SPECSIG"/><fbinput id="FB3_I4" signal="miscControlsdelay_reg0_SPECSIG"/><fbinput id="FB3_I5" signal="miscControlsdelay_reg10_SPECSIG"/><fbinput id="FB3_I6" signal="miscControlsdelay_reg11_SPECSIG"/><fbinput id="FB3_I7" signal="miscControlsdelay_reg12_SPECSIG"/><fbinput id="FB3_I8" signal="miscControlsdelay_reg13_SPECSIG"/><fbinput id="FB3_I9" signal="miscControlsdelay_reg14_SPECSIG"/><fbinput id="FB3_I10" signal="miscControlsdelay_reg15_SPECSIG"/><fbinput id="FB3_I11" signal="miscControlsdelay_reg16_SPECSIG"/><fbinput id="FB3_I12" signal="miscControlsdelay_reg17_SPECSIG"/><fbinput id="FB3_I13" signal="miscControlsdelay_reg18_SPECSIG"/><fbinput id="FB3_I14" signal="miscControlsdelay_reg1_SPECSIG"/><fbinput id="FB3_I15" signal="miscControlsdelay_reg2_SPECSIG"/><fbinput id="FB3_I16" signal="miscControlsdelay_reg3_SPECSIG"/><fbinput id="FB3_I17" signal="miscControlsdelay_reg4_SPECSIG"/><fbinput id="FB3_I18" signal="miscControlsdelay_reg5_SPECSIG"/><fbinput id="FB3_I19" signal="miscControlsdelay_reg6_SPECSIG"/><fbinput id="FB3_I20" signal="miscControlsdelay_reg7_SPECSIG"/><fbinput id="FB3_I21" signal="miscControlsdelay_reg8_SPECSIG"/><fbinput id="FB3_I22" signal="miscControlsdelay_reg9_SPECSIG"/><fbinput id="FB3_I23" signal="pgood"/><fbinput id="FB3_I24" signal="qie_reset_out_intClk_intCtrl"/><fbinput id="FB3_I25" signal="reset_out_intClk_intCtrl"/><fbinput id="FB3_I26" signal="reset_switch"/><PAL><pterm id="FB3_0"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg17_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg9_SPECSIG"/></pterm><pterm id="FB3_1"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/></pterm><pterm id="FB3_2"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg17_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg9_SPECSIG"/></pterm><pterm id="FB3_3"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/></pterm><pterm id="FB3_4"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG"/><signal id="miscControlsdelay_reg17_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg9_SPECSIG"/></pterm><pterm id="FB3_5"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/></pterm><pterm id="FB3_6"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG"/><signal id="miscControlsdelay_reg17_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/></pterm><pterm id="FB3_7"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG"/><signal id="miscControlsdelay_reg15_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/></pterm><pterm id="FB3_8"><signal id="reset_switch" negated="ON"/></pterm><pterm id="FB3_9"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG"/><signal id="miscControlsdelay_reg17_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg16_SPECSIG"/></pterm><pterm id="FB3_10"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG"/><signal id="miscControlsdelay_reg15_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG"/></pterm><pterm id="FB3_12"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/></pterm><pterm id="FB3_14"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG"/><signal id="miscControlsdelay_reg12_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG"/><signal id="miscControlsdelay_reg17_SPECSIG"/><signal id="miscControlsdelay_reg15_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG"/></pterm><pterm id="FB3_16"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/></pterm><pterm id="FB3_18"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/></pterm><pterm id="FB3_20"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/></pterm><pterm id="FB3_22"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/></pterm><pterm id="FB3_26"><signal id="pgood"/></pterm><pterm id="FB3_34"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="N_PZ_303"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/></pterm><pterm id="FB3_36"><signal id="qie_reset_out_intClk_intCtrl" negated="ON"/><signal id="fcl_intClk_intCtrlupcout0_SPECSIG"/><signal id="reset_out_intClk_intCtrl" negated="ON"/></pterm><pterm id="FB3_38"><signal id="reset_switch"/><signal id="GPIO_Extra0" negated="ON"/></pterm></PAL><bct id="FB3_bct0" use=""/><bct id="FB3_bct1" use=""/><bct id="FB3_bct2" use=""/><bct id="FB3_bct3" use=""/><bct id="FB3_bct4" use=""/><bct id="FB3_bct5" use=""/><bct id="FB3_bct6" use=""/><bct id="FB3_bct7" use=""/><equation id="reset_out_intClk_intCtrl"><d1><eq_pterm ptindx="FB3_8"/></d1><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg17_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_9"/><eq_pterm ptindx="FB3_10"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg12_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB3_12"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg18_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB3_14"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg11_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB3_16"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg9_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB3_18"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg7_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB3_20"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg6_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB3_22"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg16_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_6"/><eq_pterm ptindx="FB3_7"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="aux_out"><d1><eq_pterm ptindx="FB3_26"/></d1></equation><equation id="miscControlsdelay_reg15_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_4"/><eq_pterm ptindx="FB3_5"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg14_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_2"/><eq_pterm ptindx="FB3_3"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg13_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_0"/><eq_pterm ptindx="FB3_1"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg5_SPECSIG" regUse="T"><d1><eq_pterm ptindx="FB3_34"/></d1><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="fcl_intClk_intCtrlupcout0_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB3_36"/></d1><clk><fastsig signal="int_clk_in"/></clk><prld ptindx="GND"/></equation><equation id="reset_out_extClk_extCtrl" negated="ON"><d1><eq_pterm ptindx="FB3_38"/></d1><clk><fastsig signal="ext_clk_in"/></clk><prld ptindx="GND"/></equation></fblock><fblock id="FB4" pinUse="2"><macrocell id="FB4_MC1" pin="FB4_MC1_PIN7" sigUse="2" signal="reset_out_intClk_extCtrl"><eq_pterm ptindx="FB4_8"/></macrocell><macrocell id="FB4_MC2" pin="FB4_MC2_PIN8" sigUse="1" signal="peltEnab1"><eq_pterm ptindx="FB4_10"/></macrocell><macrocell id="FB4_MC3"/><macrocell id="FB4_MC4" pin="FB4_MC4_PIN10"/><macrocell id="FB4_MC5" pin="FB4_MC5_PIN11" sigUse="1" signal="peltEnab2"><eq_pterm ptindx="FB4_16"/></macrocell><macrocell id="FB4_MC6"/><macrocell id="FB4_MC7"/><macrocell id="FB4_MC8" sigUse="12" signal="N_PZ_303"><eq_pterm ptindx="FB4_15"/><eq_pterm ptindx="FB4_19"/><eq_pterm ptindx="FB4_13"/><eq_pterm ptindx="FB4_14"/><eq_pterm ptindx="FB4_18"/><eq_pterm ptindx="FB4_17"/></macrocell><macrocell id="FB4_MC9" pin="FB4_MC9_PIN12"/><macrocell id="FB4_MC10" pin="FB4_MC10_PIN13"/><macrocell id="FB4_MC11" pin="FB4_MC11_PIN14"/><macrocell id="FB4_MC12" pin="FB4_MC12_PIN15"/><macrocell id="FB4_MC13" sigUse="18" signal="miscControlsdelay_reg8_SPECSIG"><eq_pterm ptindx="FB4_9"/><eq_pterm ptindx="FB4_12"/><eq_pterm ptindx="FB4_6"/><eq_pterm ptindx="FB4_7"/><eq_pterm ptindx="FB4_11"/></macrocell><macrocell id="FB4_MC14" sigUse="18" signal="miscControlsdelay_reg10_SPECSIG"><eq_pterm ptindx="FB4_4"/><eq_pterm ptindx="FB4_5"/><eq_pterm ptindx="FB4_2"/><eq_pterm ptindx="FB4_3"/></macrocell><macrocell id="FB4_MC15" sigUse="14" signal="miscControlspenable_reg_SPECSIG"><eq_pterm ptindx="FB4_1"/><eq_pterm ptindx="FB4_0"/></macrocell><macrocell id="FB4_MC16" sigUse="14" signal="miscControlsdelay_reg0_SPECSIG"><eq_pterm ptindx="FB4_1"/><eq_pterm ptindx="FB4_0"/></macrocell><fbinput id="FB4_I1" signal="GPIO_Extra0"/><fbinput id="FB4_I2" signal="N_PZ_303"/><fbinput id="FB4_I3" signal="aux2"/><fbinput id="FB4_I4" signal="aux3"/><fbinput id="FB4_I5" signal="miscControlsdelay_reg0_SPECSIG"/><fbinput id="FB4_I6" signal="miscControlsdelay_reg10_SPECSIG"/><fbinput id="FB4_I7" signal="miscControlsdelay_reg11_SPECSIG"/><fbinput id="FB4_I8" signal="miscControlsdelay_reg12_SPECSIG"/><fbinput id="FB4_I9" signal="miscControlsdelay_reg13_SPECSIG"/><fbinput id="FB4_I10" signal="miscControlsdelay_reg14_SPECSIG"/><fbinput id="FB4_I11" signal="miscControlsdelay_reg15_SPECSIG"/><fbinput id="FB4_I12" signal="miscControlsdelay_reg16_SPECSIG"/><fbinput id="FB4_I13" signal="miscControlsdelay_reg17_SPECSIG"/><fbinput id="FB4_I14" signal="miscControlsdelay_reg18_SPECSIG"/><fbinput id="FB4_I15" signal="miscControlsdelay_reg1_SPECSIG"/><fbinput id="FB4_I16" signal="miscControlsdelay_reg2_SPECSIG"/><fbinput id="FB4_I17" signal="miscControlsdelay_reg3_SPECSIG"/><fbinput id="FB4_I18" signal="miscControlsdelay_reg4_SPECSIG"/><fbinput id="FB4_I19" signal="miscControlsdelay_reg5_SPECSIG"/><fbinput id="FB4_I20" signal="miscControlsdelay_reg6_SPECSIG"/><fbinput id="FB4_I21" signal="miscControlsdelay_reg7_SPECSIG"/><fbinput id="FB4_I22" signal="miscControlsdelay_reg8_SPECSIG"/><fbinput id="FB4_I23" signal="miscControlsdelay_reg9_SPECSIG"/><fbinput id="FB4_I24" signal="reset_switch"/><PAL><pterm id="FB4_0"><signal id="miscControlsdelay_reg0_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg10_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg1_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg2_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg3_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg4_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg5_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg6_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg8_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_1"><signal id="N_PZ_303"/></pterm><pterm id="FB4_2"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg12_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_4"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg17_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg9_SPECSIG"/></pterm><pterm id="FB4_5"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg8_SPECSIG"/><signal id="miscControlsdelay_reg9_SPECSIG"/><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/></pterm><pterm id="FB4_6"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg11_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_7"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg12_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_8"><signal id="reset_switch"/><signal id="GPIO_Extra0" negated="ON"/></pterm><pterm id="FB4_9"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg17_SPECSIG" negated="ON"/></pterm><pterm id="FB4_10"><signal id="aux2"/></pterm><pterm id="FB4_11"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg10_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg9_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_12"><signal id="miscControlsdelay_reg0_SPECSIG"/><signal id="miscControlsdelay_reg1_SPECSIG"/><signal id="miscControlsdelay_reg2_SPECSIG"/><signal id="miscControlsdelay_reg3_SPECSIG"/><signal id="miscControlsdelay_reg4_SPECSIG"/><signal id="miscControlsdelay_reg5_SPECSIG"/><signal id="miscControlsdelay_reg6_SPECSIG"/><signal id="miscControlsdelay_reg7_SPECSIG"/><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/></pterm><pterm id="FB4_13"><signal id="miscControlsdelay_reg11_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_14"><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg12_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_15"><signal id="miscControlsdelay_reg17_SPECSIG" negated="ON"/></pterm><pterm id="FB4_16"><signal id="aux3"/></pterm><pterm id="FB4_17"><signal id="miscControlsdelay_reg10_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg7_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg8_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_18"><signal id="miscControlsdelay_reg10_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg13_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg14_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg15_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg9_SPECSIG" negated="ON"/><signal id="miscControlsdelay_reg16_SPECSIG" negated="ON"/></pterm><pterm id="FB4_19"><signal id="miscControlsdelay_reg18_SPECSIG" negated="ON"/></pterm></PAL><bct id="FB4_bct0" use=""/><bct id="FB4_bct1" use=""/><bct id="FB4_bct2" use=""/><bct id="FB4_bct3" use=""/><bct id="FB4_bct4" use=""/><bct id="FB4_bct5" use=""/><bct id="FB4_bct6" use=""/><bct id="FB4_bct7" use=""/><equation id="reset_out_intClk_extCtrl" negated="ON"><d1><eq_pterm ptindx="FB4_8"/></d1><clk><fastsig signal="clk_in_j1"/></clk><prld ptindx="GND"/></equation><equation id="peltEnab1"><d1><eq_pterm ptindx="FB4_10"/></d1></equation><equation id="peltEnab2"><d1><eq_pterm ptindx="FB4_16"/></d1></equation><equation id="N_PZ_303"><d2><eq_pterm ptindx="FB4_15"/><eq_pterm ptindx="FB4_19"/><eq_pterm ptindx="FB4_13"/><eq_pterm ptindx="FB4_14"/><eq_pterm ptindx="FB4_18"/><eq_pterm ptindx="FB4_17"/></d2></equation><equation id="miscControlsdelay_reg8_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_9"/><eq_pterm ptindx="FB4_12"/><eq_pterm ptindx="FB4_6"/><eq_pterm ptindx="FB4_7"/><eq_pterm ptindx="FB4_11"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg10_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_4"/><eq_pterm ptindx="FB4_5"/><eq_pterm ptindx="FB4_2"/><eq_pterm ptindx="FB4_3"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlspenable_reg_SPECSIG" negated="ON"><d2><eq_pterm ptindx="FB4_1"/><eq_pterm ptindx="FB4_0"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation><equation id="miscControlsdelay_reg0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_1"/><eq_pterm ptindx="FB4_0"/></d2><clk><eq_pterm ptindx="FB1_7"/></clk><prld ptindx="GND"/></equation></fblock><vcc/><gnd/><messages><warning>Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'control_emulator.ise'.INFO:Cpld - Inferring BUFG constraint for signal 'clk_in_j1' based upon the LOC constraint 'P37'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.INFO:Cpld - Inferring BUFG constraint for signal 'ext_clk_in' based upon the LOC constraint 'P38'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.INFO:Cpld - Inferring BUFG constraint for signal 'int_clk_in' based upon the LOC constraint 'P39'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.</warning><warning>Cpld:1007 - Removing unused input(s) 'GPIO_Extra1'. The input(s) are unused after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'alt1'. The input(s) are unused after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'alt2'. The input(s) are unused after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'reset_in'. The input(s) are unused after optimization. Please verify functionality via simulation.</warning><warning>Cpld:1007 - Removing unused input(s) 'wte_in'. The input(s) are unused after optimization. Please verify functionality via simulation.</warning></messages><compOpts blkfanin="38" exhaust="OFF" fbnand="OFF" ignorets="OFF" inputs="32" inreg="ON" isp="ON" keepio="OFF" loc="ON" mlopt="ON" nouct="OFF" optimize="DENSITY" part="xcr3064xl-10-VQ44" prld="LOW" pterms="28" slew="FAST" terminate="FLOAT" unused="PULLUP" wysiwyg="OFF"/><specSig signal="b_SPECSIG" value="(b)"/><specSig signal="miscControlsdelay_reg3_SPECSIG" value="miscControls/delay_reg<3>"/><specSig signal="miscControlsdelay_reg2_SPECSIG" value="miscControls/delay_reg<2>"/><specSig signal="fcl_extClk_extCtrlhold1_SPECSIG" value="fcl_extClk_extCtrl/hold<1>"/><specSig signal="fcl_intClk_intCtrlupcout2_SPECSIG" value="fcl_intClk_intCtrl/upc/out<2>"/><specSig signal="miscControlsdelay_reg14_SPECSIG" value="miscControls/delay_reg<14>"/><specSig signal="miscControlsdelay_reg13_SPECSIG" value="miscControls/delay_reg<13>"/><specSig signal="GCKI_SPECSIG" value="GCK/I"/><specSig signal="miscControlsdelay_reg4_SPECSIG" value="miscControls/delay_reg<4>"/><specSig signal="fcl_intClk_extCtrlhold2_SPECSIG" value="fcl_intClk_extCtrl/hold<2>"/><specSig signal="fcl_intClk_extCtrlhold3_SPECSIG" value="fcl_intClk_extCtrl/hold<3>"/><specSig signal="fcl_intClk_extCtrlhold0_SPECSIG" value="fcl_intClk_extCtrl/hold<0>"/><specSig signal="miscControlsdelay_reg1_SPECSIG" value="miscControls/delay_reg<1>"/><specSig signal="fcl_extClk_extCtrlhold0_SPECSIG" value="fcl_extClk_extCtrl/hold<0>"/><specSig signal="fcl_extClk_extCtrlhold3_SPECSIG" value="fcl_extClk_extCtrl/hold<3>"/><specSig signal="fcl_intClk_extCtrlhold1_SPECSIG" value="fcl_intClk_extCtrl/hold<1>"/><specSig signal="fcl_extClk_extCtrlhold2_SPECSIG" value="fcl_extClk_extCtrl/hold<2>"/><specSig signal="miscControlsdelay_reg0_SPECSIG" value="miscControls/delay_reg<0>"/><specSig signal="miscControlspenable_reg_SPECSIG" value="miscControls/penable_reg"/><specSig signal="fcl_intClk_intCtrlupcout1_SPECSIG" value="fcl_intClk_intCtrl/upc/out<1>"/><specSig signal="fcl_intClk_intCtrlupcout3_SPECSIG" value="fcl_intClk_intCtrl/upc/out<3>"/><specSig signal="fcl_intClk_intCtrlupcout5_SPECSIG" value="fcl_intClk_intCtrl/upc/out<5>"/><specSig signal="fcl_intClk_intCtrlupcout6_SPECSIG" value="fcl_intClk_intCtrl/upc/out<6>"/><specSig signal="fcl_intClk_intCtrlupcout7_SPECSIG" value="fcl_intClk_intCtrl/upc/out<7>"/><specSig signal="fcl_intClk_intCtrlupcout8_SPECSIG" value="fcl_intClk_intCtrl/upc/out<8>"/><specSig signal="fcl_intClk_intCtrlupcout9_SPECSIG" value="fcl_intClk_intCtrl/upc/out<9>"/><specSig signal="fcl_intClk_intCtrlupcout4_SPECSIG" value="fcl_intClk_intCtrl/upc/out<4>"/><specSig signal="fcl_intClk_intCtrlupcout10_SPECSIG" value="fcl_intClk_intCtrl/upc/out<10>"/><specSig signal="fcl_intClk_intCtrlupcout11_SPECSIG" value="fcl_intClk_intCtrl/upc/out<11>"/><specSig signal="fcl_intClk_intCtrlupcout0_SPECSIG" value="fcl_intClk_intCtrl/upc/out<0>"/><specSig signal="miscControlsdelay_reg17_SPECSIG" value="miscControls/delay_reg<17>"/><specSig signal="miscControlsdelay_reg12_SPECSIG" value="miscControls/delay_reg<12>"/><specSig signal="miscControlsdelay_reg18_SPECSIG" value="miscControls/delay_reg<18>"/><specSig signal="miscControlsdelay_reg11_SPECSIG" value="miscControls/delay_reg<11>"/><specSig signal="miscControlsdelay_reg9_SPECSIG" value="miscControls/delay_reg<9>"/><specSig signal="miscControlsdelay_reg7_SPECSIG" value="miscControls/delay_reg<7>"/><specSig signal="miscControlsdelay_reg6_SPECSIG" value="miscControls/delay_reg<6>"/><specSig signal="miscControlsdelay_reg16_SPECSIG" value="miscControls/delay_reg<16>"/><specSig signal="miscControlsdelay_reg15_SPECSIG" value="miscControls/delay_reg<15>"/><specSig signal="miscControlsdelay_reg5_SPECSIG" value="miscControls/delay_reg<5>"/><specSig signal="miscControlsdelay_reg10_SPECSIG" value="miscControls/delay_reg<10>"/><specSig signal="miscControlsdelay_reg8_SPECSIG" value="miscControls/delay_reg<8>"/></document>