Refactor speaker signal chain, add analog series caps and resistors (#467)

Post-analog-compositional-passive cleanup. Adds AnalogSeriesCapacitor
and AnalogSeriesResistor library parts to eliminate the adhoc .adapt_to
in the speaker drivers.

Removes the impedance check for the speakers, since it breaks with the
modeling of the series analog resistor.

Removes the pull port form the solid-state relay which also needed an
adhoc .adapt_to and broke levels of abstraction. This is a breaking
change with no deprecation path.

Updates netlists, since AnalogSeriesCapacitor/Reisstor has inner parts
now.

Resolves #466, resolves #464

Author: ducky64

edg/abstract_parts/AbstractCapacitor.py

@@ -421,6 +421,63 @@ def connected(
         return self
 
 
+class AnalogSeriesCapacitor(DiscreteApplication, KiCadImportableBlock):
+    """Series DC-blocking capacitor for an analog signal."""
+
+    @override
+    def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]:
+        assert symbol_name in ("Device:C", "Device:C_Small", "Device:C_Polarized", "Device:C_Polarized_Small")
+        return {"1": self.input, "2": self.output}
+
+    def __init__(self, capacitance: RangeLike, output_bias: RangeLike, *, exact_capacitance: BoolLike = False) -> None:
+        super().__init__()
+
+        self.output_bias = self.ArgParameter(output_bias)
+
+        self.input = self.Port(AnalogSink(impedance=RangeExpr()), [Input])
+        self.output = self.Port(
+            AnalogSource(voltage_out=RangeExpr(), signal_out=RangeExpr(), impedance=self.input.link().source_impedance),
+            [Output],
+        )
+
+        self.cap = self.Block(
+            Capacitor(
+                capacitance,
+                voltage=self.input.link().voltage - self.output.link().voltage,
+                exact_capacitance=exact_capacitance,
+            )
+        )
+
+    @override
+    def contents(self) -> None:
+        super().contents()
+
+        self.connect(self.input.net, self.cap.neg)
+        self.connect(self.output.net, self.cap.pos)
+
+        self.assign(self.input.impedance, self.output.link().sink_impedance)  # assumed high frequency
+        voltage_halfspan = (self.input.link().voltage.upper() - self.input.link().voltage.lower()) / 2
+        self.assign(
+            self.output.voltage_out,
+            (self.output_bias.lower() - voltage_halfspan, self.output_bias.upper() + voltage_halfspan),
+        )
+        signal_halfspan = (self.input.link().signal.upper() - self.input.link().signal.lower()) / 2
+        self.assign(
+            self.output.signal_out,
+            (self.output_bias.lower() - signal_halfspan, self.output_bias.upper() + signal_halfspan),
+        )
+
+    def connected(
+        self, input: Optional[Port[AnalogLink]] = None, output: Optional[Port[AnalogLink]] = None
+    ) -> "AnalogSeriesCapacitor":
+        """Convenience function to connect both ports, returning this object so it can still be given a name."""
+        if input is not None:
+            cast(Block, builder.get_enclosing_block()).connect(input, self.input)
+        if output is not None:
+            cast(Block, builder.get_enclosing_block()).connect(output, self.output)
+        return self
+
+
 class CombinedCapacitorElement(Capacitor):  # to avoid an abstract part error
     @override
     def contents(self) -> None:

edg/abstract_parts/AbstractResistor.py

@@ -372,6 +372,49 @@ def symbol_pinning(self, symbol_name: str) -> Dict[str, Port]:
         return {"1": self.pwr_in, "2": self.pwr_out, "sense_in": self.sense_in, "sense_out": self.sense_out}
 
 
+class AnalogSeriesResistor(DiscreteApplication, KiCadImportableBlock):
+    """Analog passthrough series resistor"""
+
+    @override
+    def symbol_pinning(self, symbol_name: str) -> Mapping[str, BasePort]:
+        assert symbol_name in ("Device:R", "Device:R_Small")
+        return {"1": self.input, "2": self.output}
+
+    def __init__(self, resistance: RangeLike) -> None:
+        super().__init__()
+
+        self.res = self.Block(Resistor(resistance=resistance, power=RangeExpr()))
+        self.actual_resistance = self.Parameter(RangeExpr(self.res.actual_resistance))
+
+        self.input = self.Port(AnalogSink(impedance=RangeExpr()), [Input])
+        self.output = self.Port(
+            AnalogSource(
+                voltage_out=self.input.link().voltage,
+                signal_out=self.input.link().signal,
+                impedance=self.input.link().source_impedance + self.res.actual_resistance,
+            ),
+            [Output],
+        )
+
+        self.assign(self.input.impedance, self.output.link().sink_impedance + self.res.actual_resistance)
+
+        self.assign(
+            self.res.power, self.input.link().current_drawn * self.input.link().current_drawn * self.res.resistance
+        )
+        self.connect(self.input.net, self.res.a)
+        self.connect(self.output.net, self.res.b)
+
+    def connected(
+        self, input: Optional[Port[AnalogLink]] = None, output: Optional[Port[AnalogLink]] = None
+    ) -> "AnalogSeriesResistor":
+        """Convenience function to connect both ports, returning this object so it can still be given a name."""
+        if input is not None:
+            cast(Block, builder.get_enclosing_block()).connect(input, self.input)
+        if output is not None:
+            cast(Block, builder.get_enclosing_block()).connect(output, self.output)
+        return self
+
+
 class AnalogClampResistor(Protection, KiCadImportableBlock):
     """Inline resistor that limits the current (to a parameterized amount) which works in concert
     with ESD diodes in the downstream device to clamp the signal voltage to allowable levels.

edg/abstract_parts/AbstractSolidStateRelay.py

@@ -99,14 +99,14 @@ class AnalogIsolatedSwitch(Interface, KiCadImportableBlock, Block):
     The ports are not tagged with Input/Output/InOut, because of potential for confusion between
     the digital side and the analog side.
 
-    A separate output-side pull port allows modeling the output switch standoff voltage
-    when the switch is off.
+    The output is modeled as if the switch is closed. A weak pull-up (or down) could be modeled by
+    combining this device's output with a MergedAnalogSource.
     """
 
     @override
     def symbol_pinning(self, symbol_name: str) -> Dict[str, BasePort]:
         assert symbol_name == "edg_importable:AnalogIsolatedSwitch"
-        return {"in": self.signal, "gnd": self.gnd, "ain": self.ain, "apull": self.apull, "aout": self.aout}
+        return {"in": self.signal, "gnd": self.gnd, "ain": self.ain, "aout": self.aout}
 
     def __init__(self) -> None:
         super().__init__()
@@ -116,15 +116,27 @@ def __init__(self) -> None:
         self.signal = self.Port(DigitalSink.empty())
         self.gnd = self.Port(Ground.empty(), [Common])
 
-        self.apull = self.Port(AnalogSink.empty())
         self.ain = self.Port(
             AnalogSink(
                 voltage_limits=RangeExpr(),
                 impedance=RangeExpr(),
             )
         )
-        self.aout = self.Port(AnalogSource.empty())
-        self.assign(self.ain.voltage_limits, self.apull.link().voltage + self.ic.load_voltage_limit)
+        self.aout = self.Port(
+            AnalogSource(
+                voltage_out=self.ain.link().voltage,
+                signal_out=self.ain.link().signal,
+                current_limits=self.ic.load_current_limit,
+                impedance=self.ain.link().source_impedance + self.ic.load_resistance,
+            )
+        )
+        self.assign(
+            self.ain.voltage_limits,
+            (
+                self.aout.link().voltage.lower() + self.ic.load_voltage_limit.upper(),
+                self.aout.link().voltage.upper() - self.ic.load_voltage_limit.lower(),
+            ),
+        )
         self.assign(self.ain.impedance, self.aout.link().sink_impedance + self.ic.load_resistance)
 
         self.res = self.Block(
@@ -143,15 +155,4 @@ def __init__(self) -> None:
         self.connect(self.res.b.adapt_to(Ground()), self.gnd)
 
         self.connect(self.ain.net, self.ic.feta)
-        self.pull_merge = self.Block(MergedAnalogSource()).connected_from(
-            self.apull,
-            self.ic.fetb.adapt_to(
-                AnalogSource(
-                    voltage_out=self.ain.link().voltage,
-                    signal_out=self.ain.link().signal,
-                    current_limits=self.ic.load_current_limit,
-                    impedance=self.ain.link().source_impedance + self.ic.load_resistance,
-                )
-            ),
-        )
-        self.connect(self.pull_merge.output, self.aout)
+        self.connect(self.aout.net, self.ic.fetb)

edg/abstract_parts/__init__.py

@@ -52,7 +52,7 @@
     SmaMConnector,
     SmaFConnector,
 )
-from .AbstractResistor import Resistor, ResistorStandardFootprint, TableResistor, SeriesResistor
+from .AbstractResistor import Resistor, ResistorStandardFootprint, TableResistor, SeriesResistor, AnalogSeriesResistor
 from .AbstractResistor import PulldownResistor, PullupResistor, PulldownResistorArray, PullupResistorArray
 from .AbstractResistor import SeriesPowerResistor, CurrentSenseResistor, AnalogClampResistor, DigitalClampResistor
 from .AbstractResistorArray import ResistorArray, ResistorArrayStandardFootprint, TableResistorArray
@@ -65,7 +65,13 @@
     TableCapacitor,
     TableDeratingCapacitor,
 )
-from .AbstractCapacitor import DummyCapacitorFootprint, DecouplingCapacitor, AnalogCapacitor, CombinedCapacitor
+from .AbstractCapacitor import (
+    DummyCapacitorFootprint,
+    DecouplingCapacitor,
+    AnalogCapacitor,
+    AnalogSeriesCapacitor,
+    CombinedCapacitor,
+)
 from .AbstractInductor import Inductor, TableInductor, SeriesPowerInductor
 from .AbstractFerriteBead import FerriteBead, FerriteBeadStandardFootprint, TableFerriteBead, SeriesPowerFerriteBead
 from .ResistiveDivider import ResistiveDivider, VoltageDivider, VoltageSenseDivider

edg/parts/SpeakerDriver_Analog.py

@@ -112,7 +112,8 @@ def __init__(self) -> None:
             self.pwr,
             voltage_limit_tolerance=(-0.3, 0.3) * Volt,
             signal_limit_bound=(0.5 * Volt, -0.8 * Volt),
-            impedance=(142, 158) * kOhm,
+            # TODO this is too low for the input resistor and the analog link assertion, but signal attenuation is fine in practice
+            # impedance=(142, 158) * kOhm,
         )
         self.inp = self.Port(input_port)
         self.inn = self.Port(input_port)
@@ -151,15 +152,15 @@ class Tpa2005d1(SpeakerDriver, Block):
     """TPA2005D1 configured in single-ended input mode.
     Possible semi-pin-compatible with PAM8302AASCR (C113367), but which has internal resistor."""
 
-    def __init__(self, gain: RangeLike = Range.from_tolerance(20, 0.2)):
+    def __init__(self, gain: RangeLike = 20 * Ratio(tol=0.2)):
         super().__init__()
         # TODO should be a SpeakerDriver abstract part
 
         self.ic = self.Block(Tpa2005d1_Device())
         self.pwr = self.Export(self.ic.pwr, [Power])
         self.gnd = self.Export(self.ic.gnd, [Common])
 
-        self.sig = self.Port(AnalogSink(), [Input])
+        self.sig = self.Port(AnalogSink.empty(), [Input])
         self.spk = self.Export(self.ic.vo, [Output])
 
         self.gain = self.ArgParameter(gain)
@@ -185,34 +186,31 @@ def contents(self) -> None:
 
         # Note, gain = 2 * (142k to 158k)/Ri, recommended gain < 20V/V
         res_value = (1 / self.gain).shrink_multiply(2 * Range(142e3, 158e3))
-        in_res_model = Resistor(res_value)
+        in_res_model = AnalogSeriesResistor(res_value)
         fc = (1, 20) * Hertz  # for highpass filter, arbitrary, 20Hz right on the edge of audio frequency
+        in_bias_voltage = self.pwr.link().voltage / 2  # assumed input bias point
 
         self.inp_res = self.Block(in_res_model)
         self.inp_cap = self.Block(
-            Capacitor(
+            AnalogSeriesCapacitor(
                 capacitance=(1 / (2 * math.pi * fc))
                 .shrink_multiply(1 / self.inp_res.actual_resistance)
                 .intersect((1 * 0.8, float("inf")) * uFarad),
-                voltage=self.sig.link().voltage,
+                output_bias=in_bias_voltage,
             )
         )
-        self.connect(self.sig.net, self.inp_cap.neg)
-        self.connect(self.inp_cap.pos, self.inp_res.a)
-        self.connect(self.inp_res.b.adapt_to(AnalogSource()), self.ic.inp)
+        self.chain(self.sig, self.inp_cap, self.inp_res, self.ic.inp)
 
         self.inn_res = self.Block(in_res_model)
         self.inn_cap = self.Block(
-            Capacitor(
+            AnalogSeriesCapacitor(
                 capacitance=(1 / (2 * math.pi * fc))
                 .shrink_multiply(1 / self.inn_res.actual_resistance)
                 .intersect((1 * 0.8, float("inf")) * uFarad),
-                voltage=self.sig.link().voltage,
+                output_bias=in_bias_voltage,
             )
         )
-        self.connect(self.gnd, self.inn_cap.neg.adapt_to(Ground()))
-        self.connect(self.inn_cap.pos, self.inn_res.a)
-        self.connect(self.inn_res.b.adapt_to(AnalogSource()), self.ic.inn)
+        self.chain(self.gnd.as_analog_source(), self.inn_cap, self.inn_res, self.ic.inn)
 
 
 class Pam8302a_Device(InternalSubcircuit, JlcPart, FootprintBlock):
@@ -291,10 +289,8 @@ def contents(self) -> None:
             )
         ).connected(self.gnd, self.pwr)
 
-        in_cap_model = Capacitor(capacitance=0.1 * uFarad(tol=0.2), voltage=self.sig.link().voltage)
-        self.inp_cap = self.Block(in_cap_model)
-        self.connect(self.sig, self.inp_cap.neg.adapt_to(AnalogSink()))
-        self.connect(self.inp_cap.pos.adapt_to(AnalogSource()), self.ic.inp)
-        self.inn_cap = self.Block(in_cap_model)
-        self.connect(self.gnd, self.inn_cap.neg.adapt_to(Ground()))
-        self.connect(self.inn_cap.pos.adapt_to(AnalogSource()), self.ic.inn)
+        input_cap_model = AnalogSeriesCapacitor(
+            capacitance=0.1 * uFarad(tol=0.2), output_bias=self.pwr.link().voltage / 2
+        )
+        self.inp_cap = self.Block(input_cap_model).connected(self.sig, self.ic.inp)
+        self.inn_cap = self.Block(input_cap_model).connected(self.gnd.as_analog_source(), self.ic.inn)

examples/DeskController/DeskController.net

@@ -653,7 +653,7 @@
   (footprint "Resistor_SMD:R_0603_1608Metric")
   (property (name "Sheetname") (value "spk_drv"))
   (property (name "Sheetfile") (value "edg.parts.SpeakerDriver_Analog.Tpa2005d1"))
-  (property (name "edg_path") (value "spk_drv.inp_res"))
+  (property (name "edg_path") (value "spk_drv.inp_res.res"))
   (property (name "edg_short_path") (value "spk_drv.inp_res"))
   (property (name "edg_refdes") (value "DR10"))
   (property (name "edg_part") (value "0603WAF6802T5E (UNI-ROYAL(Uniroyal Elec))"))
@@ -665,7 +665,7 @@
   (footprint "Capacitor_SMD:C_0603_1608Metric")
   (property (name "Sheetname") (value "spk_drv"))
   (property (name "Sheetfile") (value "edg.parts.SpeakerDriver_Analog.Tpa2005d1"))
-  (property (name "edg_path") (value "spk_drv.inp_cap"))
+  (property (name "edg_path") (value "spk_drv.inp_cap.cap"))
   (property (name "edg_short_path") (value "spk_drv.inp_cap"))
   (property (name "edg_refdes") (value "DC15"))
   (property (name "edg_part") (value "CL10A105KB8NNNC (Samsung Electro-Mechanics)"))
@@ -677,7 +677,7 @@
   (footprint "Resistor_SMD:R_0603_1608Metric")
   (property (name "Sheetname") (value "spk_drv"))
   (property (name "Sheetfile") (value "edg.parts.SpeakerDriver_Analog.Tpa2005d1"))
-  (property (name "edg_path") (value "spk_drv.inn_res"))
+  (property (name "edg_path") (value "spk_drv.inn_res.res"))
   (property (name "edg_short_path") (value "spk_drv.inn_res"))
   (property (name "edg_refdes") (value "DR11"))
   (property (name "edg_part") (value "0603WAF6802T5E (UNI-ROYAL(Uniroyal Elec))"))
@@ -689,7 +689,7 @@
   (footprint "Capacitor_SMD:C_0603_1608Metric")
   (property (name "Sheetname") (value "spk_drv"))
   (property (name "Sheetfile") (value "edg.parts.SpeakerDriver_Analog.Tpa2005d1"))
-  (property (name "edg_path") (value "spk_drv.inn_cap"))
+  (property (name "edg_path") (value "spk_drv.inn_cap.cap"))
   (property (name "edg_short_path") (value "spk_drv.inn_cap"))
   (property (name "edg_refdes") (value "DC16"))
   (property (name "edg_part") (value "CL10A105KB8NNNC (Samsung Electro-Mechanics)"))
@@ -1115,10 +1115,10 @@
 (net (code 40) (name "Dspk_drv.ic.inn")
   (node (ref DU4) (pin 3))
   (node (ref DR11) (pin 2)))
-(net (code 41) (name "Dspk_drv.inp_res.a")
+(net (code 41) (name "Dspk_drv.inp_res.input")
   (node (ref DR10) (pin 1))
   (node (ref DC15) (pin 1)))
-(net (code 42) (name "Dspk_drv.inn_res.a")
+(net (code 42) (name "Dspk_drv.inn_res.input")
   (node (ref DR11) (pin 1))
   (node (ref DC16) (pin 1)))
 (net (code 43) (name "Dnpx_shift.lv_io")

examples/DeskController/DeskController.svgpcb.js

@@ -211,22 +211,22 @@ const DC14 = board.add(C_0805_2012Metric, {
   translate: pt(0.352, 3.279), rotate: 0,
   id: 'DC14'
 })
-// spk_drv.inp_res
+// spk_drv.inp_res.res
 const DR10 = board.add(R_0603_1608Metric, {
   translate: pt(0.214, 3.446), rotate: 0,
   id: 'DR10'
 })
-// spk_drv.inp_cap
+// spk_drv.inp_cap.cap
 const DC15 = board.add(C_0603_1608Metric, {
   translate: pt(0.370, 3.446), rotate: 0,
   id: 'DC15'
 })
-// spk_drv.inn_res
+// spk_drv.inn_res.res
 const DR11 = board.add(R_0603_1608Metric, {
   translate: pt(0.058, 3.543), rotate: 0,
   id: 'DR11'
 })
-// spk_drv.inn_cap
+// spk_drv.inn_cap.cap
 const DC16 = board.add(C_0603_1608Metric, {
   translate: pt(0.214, 3.543), rotate: 0,
   id: 'DC16'
@@ -353,8 +353,8 @@ board.setNetlist([
   {name: "Doled.device.c2n", pads: [["DJ3", "28"], ["DC7", "2"]]},
   {name: "Dspk_drv.ic.inp", pads: [["DU4", "4"], ["DR10", "2"]]},
   {name: "Dspk_drv.ic.inn", pads: [["DU4", "3"], ["DR11", "2"]]},
-  {name: "Dspk_drv.inp_res.a", pads: [["DR10", "1"], ["DC15", "1"]]},
-  {name: "Dspk_drv.inn_res.a", pads: [["DR11", "1"], ["DC16", "1"]]},
+  {name: "Dspk_drv.inp_res.input", pads: [["DR10", "1"], ["DC15", "1"]]},
+  {name: "Dspk_drv.inn_res.input", pads: [["DR11", "1"], ["DC16", "1"]]},
   {name: "Dnpx_shift.lv_io", pads: [["DU2", "6"], ["DQ3", "2"]]},
   {name: "Dnpx_shift.hv_io", pads: [["DQ3", "3"], ["DR12", "2"], ["DTP5", "1"], ["DD9", "4"]]},
   {name: "Dnpx.dout", pads: [["DD14", "2"]]},

examples/IotKnob/IotKnob.net

@@ -1577,7 +1577,7 @@
   (footprint "Capacitor_SMD:C_0603_1608Metric")
   (property (name "Sheetname") (value "spk_drv"))
   (property (name "Sheetfile") (value "edg.parts.SpeakerDriver_Analog.Pam8302a"))
-  (property (name "edg_path") (value "spk_drv.inp_cap"))
+  (property (name "edg_path") (value "spk_drv.inp_cap.cap"))
   (property (name "edg_short_path") (value "spk_drv.inp_cap"))
   (property (name "edg_refdes") (value "KC55"))
   (property (name "edg_part") (value "CC0603KRX7R9BB104 (YAGEO)"))
@@ -1589,7 +1589,7 @@
   (footprint "Capacitor_SMD:C_0603_1608Metric")
   (property (name "Sheetname") (value "spk_drv"))
   (property (name "Sheetfile") (value "edg.parts.SpeakerDriver_Analog.Pam8302a"))
-  (property (name "edg_path") (value "spk_drv.inn_cap"))
+  (property (name "edg_path") (value "spk_drv.inn_cap.cap"))
   (property (name "edg_short_path") (value "spk_drv.inn_cap"))
   (property (name "edg_refdes") (value "KC56"))
   (property (name "edg_part") (value "CC0603KRX7R9BB104 (YAGEO)"))